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| author | Alex Deucher <alexander.deucher@amd.com> | 2012-11-08 10:08:04 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-11-17 13:16:34 -0800 |
| commit | c436fd2bc1d4255f888dfd68a9f73098cebf30a7 (patch) | |
| tree | 4c86a0e22b6f387f65b54a5063db46d5266ebc90 /drivers | |
| parent | 4fa1f62322efae688e5412a6e483777553898cf6 (diff) | |
| download | linux-3.10-c436fd2bc1d4255f888dfd68a9f73098cebf30a7.tar.gz linux-3.10-c436fd2bc1d4255f888dfd68a9f73098cebf30a7.tar.bz2 linux-3.10-c436fd2bc1d4255f888dfd68a9f73098cebf30a7.zip | |
drm/radeon/cayman: add some missing regs to the VM reg checker
commit 860fe2f05fa2eacac84368e23547ec8cf3cc6652 upstream.
These regs were being wronly rejected leading to rendering
issues.
fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=56876
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_cs.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index 977b22d4f47..22c84bcfaeb 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c @@ -2671,6 +2671,9 @@ static bool evergreen_vm_reg_valid(u32 reg) /* check config regs */ switch (reg) { case GRBM_GFX_INDEX: + case CP_STRMOUT_CNTL: + case CP_COHER_CNTL: + case CP_COHER_SIZE: case VGT_VTX_VECT_EJECT_REG: case VGT_CACHE_INVALIDATION: case VGT_GS_VERTEX_REUSE: diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index f62ccd3555d..2eaaea061d6 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -77,6 +77,10 @@ #define CONFIG_MEMSIZE 0x5428 +#define CP_STRMOUT_CNTL 0x84FC + +#define CP_COHER_CNTL 0x85F0 +#define CP_COHER_SIZE 0x85F4 #define CP_COHER_BASE 0x85F8 #define CP_ME_CNTL 0x86D8 #define CP_ME_HALT (1 << 28) |