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author | Pauli Nieminen <suokkos@gmail.com> | 2010-02-04 19:20:53 +0200 |
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committer | Dave Airlie <airlied@redhat.com> | 2010-02-05 11:45:10 +1000 |
commit | 9e5b2af75abc67c13005c706cf95bbbb78f7fddc (patch) | |
tree | 8f8d93c115ad986486e7aab702700c2e263ff8bb /drivers | |
parent | 062b389c8704e539e234cfd67c7e034a514f50bf (diff) | |
download | linux-3.10-9e5b2af75abc67c13005c706cf95bbbb78f7fddc.tar.gz linux-3.10-9e5b2af75abc67c13005c706cf95bbbb78f7fddc.tar.bz2 linux-3.10-9e5b2af75abc67c13005c706cf95bbbb78f7fddc.zip |
drm/r100/kms: Emit cache flush to the end of command buffer. (v2)
Cache flush is required in case CPU is accessing rendered data.
This fixes glean/readPixSanity test case and random rendering
errors in sauerbraten and warzone2100.
v2 Fix comment ordering in r100_fence_ring_emit and remove extra
defines added in first version.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 11c9a3fe681..626e79023e3 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -354,11 +354,17 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) return RREG32(RADEON_CRTC2_CRNT_FRAME); } +/* Who ever call radeon_fence_emit should call ring_lock and ask + * for enough space (today caller are ib schedule and buffer move) */ void r100_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { - /* Who ever call radeon_fence_emit should call ring_lock and ask - * for enough space (today caller are ib schedule and buffer move) */ + /* We have to make sure that caches are flushed before + * CPU might read something from VRAM. */ + radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); + radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); /* Wait until IDLE & CLEAN */ radeon_ring_write(rdev, PACKET0(0x1720, 0)); radeon_ring_write(rdev, (1 << 16) | (1 << 17)); |