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authorInki Dae <inki.dae@samsung.com>2014-09-24 00:33:11 +0900
committerChanho Park <chanho61.park@samsung.com>2014-11-18 12:00:50 +0900
commitea2e861e7c8ef8aed39c62039c0ff74b1f39a73a (patch)
treefae42b5ceb5788edf93033430d04be07ccf493b9 /drivers
parentacd86ca98fcefeae1d4cdc8f8b4f87e66fed5496 (diff)
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drm/exynos: fimd: fix screen shaking issue
This patch fixes the issue that the screen is shared once resume. The issue could be incurred when overlay registers are updated by win_commit while transmitting video data. So this patch makes win_commit function wait for vsync signal if fimd is still transmitting video data before updating overlay registers. Change-Id: Ia5efff85ccad91cd6e8ff7a5e167a883c8e8d4aa Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 6e5e1a84d72..e7cc2ab311a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -636,6 +636,25 @@ static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
}
/*
+ * Wait for the completion of current transmission if fimd is still
+ * transmitting video data.
+ *
+ * Below codes resolve following issue:
+ * when resumed, fimd_win_commit() could be called to update overlay
+ * relevent registers and then pae flip could be performed by userspace
+ * request. The problem is that te interrupt could occur and
+ * fimd_trigger() could be called before fimd_win_commit is called by
+ * page flip function, exynos_drm_crtc_page_flip.
+ *
+ * In this case, there is a problem that fimd_win_commit() is called by
+ * the page flip request while fimd is still transmitting video data
+ * so overlay registers are updated to new buffer. That makes screen
+ * to be shaked.
+ */
+ if (ctx->i80_if && atomic_read(&ctx->triggering))
+ fimd_wait_for_vblank(mgr);
+
+ /*
* SHADOWCON/PRTCON register is used for enabling timing.
*
* for example, once only width value of a register is set,