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authorThomas Abraham <thomas.abraham@linaro.org>2013-03-09 17:10:31 +0900
committerKukjin Kim <kgene.kim@samsung.com>2013-03-25 18:17:14 +0900
commit415ac2e240f7f3e1b609f34ba7aa1c340589fdb1 (patch)
tree31aec92707983e1f0d9bf46627f673d2d603dc35 /drivers
parentee6c7137d74f29de2c9b81f759ed1fbbd6c4a3d1 (diff)
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clocksource: mct: use fin_pll clock as the tick clock source for mct
With the migration of Exynos4 clocks to use common clock framework, the old styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used as the tick clock for mct controller. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clocksource/exynos_mct.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 545c98976e9..f817c540126 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -479,10 +479,13 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
- struct clk *mct_clk;
- mct_clk = clk_get(NULL, "xtal");
+ struct clk *tick_clk;
- clk_rate = clk_get_rate(mct_clk);
+ tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
+ clk_get(NULL, "fin_pll");
+ if (IS_ERR(tick_clk))
+ panic("%s: unable to determine tick clock rate\n", __func__);
+ clk_rate = clk_get_rate(tick_clk);
reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
if (!reg_base)