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authorJaehoon Chung <jh80.chung@samsung.com>2013-07-24 14:11:08 +0900
committerChanho Park <chanho61.park@samsung.com>2014-11-18 11:43:42 +0900
commitddcfb86cbbf1d2ab980020978a02868b5e9d002f (patch)
tree38802df838f17255c6cb6ff82ff043689326af3c /drivers
parentfff0217d5679c8cf51f8d8b3a7f4d0aa16de0437 (diff)
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clock: clk-exynos4: set the CLK_SET_RATE_PARENT for mmc4
mmc4_clk set to CLK_SET_PARENT with DIV_F(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 43442522bb1..45ddd0ddf13 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -525,7 +525,6 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
- DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
@@ -552,6 +551,8 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
};
/* list of divider clocks supported in exynos4210 soc */