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| author | Myron Stowe <mstowe@redhat.com> | 2011-10-28 15:48:38 -0600 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-01-06 12:10:42 -0800 |
| commit | 96c5590058d7fded14f43af2ab521436cecf3125 (patch) | |
| tree | 673577f86b1ee8886c27cc86333fdfdc6cc783ac /drivers/pci | |
| parent | 9cdce18d6f0baae53f012fb3f50e66e7ff24c509 (diff) | |
| download | linux-3.10-96c5590058d7fded14f43af2ab521436cecf3125.tar.gz linux-3.10-96c5590058d7fded14f43af2ab521436cecf3125.tar.bz2 linux-3.10-96c5590058d7fded14f43af2ab521436cecf3125.zip | |
PCI: Pull PCI 'latency timer' setup up into the core
The 'latency timer' of PCI devices, both Type 0 and Type 1,
is setup in architecture-specific code [see: 'pcibios_set_master()'].
There are two approaches being taken by all the architectures - check
if the 'latency timer' is currently set between 16 and 255 and if not
bring it within bounds, or, do nothing (and then there is the
gratuitously different PA-RISC implementation).
There is nothing architecture-specific about PCI's 'latency timer' so
this patch pulls its setup functionality up into the PCI core by
creating a generic 'pcibios_set_master()' function using the '__weak'
attribute which can be used by all architectures as a default which,
if necessary, can then be over-ridden by architecture-specific code.
No functional change.
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 924193ef4fe..f9abe84cf5e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -88,6 +88,12 @@ enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; u8 pci_cache_line_size; +/* + * If we set up a device for bus mastering, we need to check the latency + * timer as certain BIOSes forget to set it properly. + */ +unsigned int pcibios_max_latency = 255; + /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children * @bus: pointer to PCI bus structure to search @@ -2596,6 +2602,29 @@ static void __pci_set_master(struct pci_dev *dev, bool enable) } /** + * pcibios_set_master - enable PCI bus-mastering for device dev + * @dev: the PCI device to enable + * + * Enables PCI bus-mastering for the device. This is the default + * implementation. Architecture specific implementations can override + * this if necessary. + */ +void __weak pcibios_set_master(struct pci_dev *dev) +{ + u8 lat; + + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); + if (lat < 16) + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; + else if (lat > pcibios_max_latency) + lat = pcibios_max_latency; + else + return; + dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); +} + +/** * pci_set_master - enables bus-mastering for device dev * @dev: the PCI device to enable * |