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authorMichael Chan <mchan@broadcom.com>2006-03-20 22:28:05 -0800
committerDavid S. Miller <davem@davemloft.net>2006-03-20 22:28:05 -0800
commit5a6f3074c2ea5a7b4ff5b18f0e1fd9b1257e1a29 (patch)
tree4bc683f620e3176ae70932f5f865fe47423eb083 /drivers/net/tg3.h
parent1b27777a9b9b2b6d1c06000b7a31262d198b4238 (diff)
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[TG3]: Add new hard_start_xmit
Support 5787 hardware TSO using a new flag TG3_FLG2_HW_TSO_2. Since the TSO interface is slightly different and these chips have finally fixed the 4GB DMA problem and do not have the 40-bit DMA problem, a new hard_start_xmit is used for these chips. All previous chips will use the old hard_start_xmit that is now renamed tg3_start_xmit_dma_bug(). Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 6a0d2fa0574..ba3466c8a96 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2194,7 +2194,7 @@ struct tg3 {
#define TG3_FLG2_PHY_SERDES 0x00002000
#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
#define TG3_FLG2_FLASH 0x00008000
-#define TG3_FLG2_HW_TSO 0x00010000
+#define TG3_FLG2_HW_TSO_1 0x00010000
#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
#define TG3_FLG2_5705_PLUS 0x00040000
#define TG3_FLG2_5750_PLUS 0x00080000
@@ -2207,6 +2207,8 @@ struct tg3 {
#define TG3_FLG2_PARALLEL_DETECT 0x01000000
#define TG3_FLG2_ICH_WORKAROUND 0x02000000
#define TG3_FLG2_5780_CLASS 0x04000000
+#define TG3_FLG2_HW_TSO_2 0x08000000
+#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3