diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-09-30 10:34:31 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-10-01 00:24:42 -0700 |
| commit | d309a46e42542223946d3a9e4e239fdc945cb53e (patch) | |
| tree | 43fae359546e61d0bda67d903d03db11d227033c /drivers/net/tg3.c | |
| parent | 66cfd1bd05a7a1c31c9cdbb2ddf5c57d1cddc5f6 (diff) | |
| download | linux-3.10-d309a46e42542223946d3a9e4e239fdc945cb53e.tar.gz linux-3.10-d309a46e42542223946d3a9e4e239fdc945cb53e.tar.bz2 linux-3.10-d309a46e42542223946d3a9e4e239fdc945cb53e.zip | |
tg3: 5719: Prevent tx data corruption
This patch enables a bit that prevents read DMA overflows and adjusts
the txmbuf margin from the hardware default. The combination of these
modifications prevents a tx data corruption issue we were seeing on the
5719.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 982ed44f075..b6388be1cd1 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7857,7 +7857,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(BUFMGR_DMA_HIGH_WATER, tp->bufmgr_config.dma_high_water); - tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) + val |= BUFMGR_MODE_NO_TX_UNDERRUN; + tw32(BUFMGR_MODE, val); for (i = 0; i < 2000; i++) { if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) break; @@ -8037,6 +8040,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); } + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { + val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); + tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | + TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | + TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); + } + /* Receive/send statistics. */ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { val = tr32(RCVLPC_STATS_ENABLE); |