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authorMarek Szyprowski <m.szyprowski@samsung.com>2015-02-26 09:55:32 +0100
committerMarek Szyprowski <m.szyprowski@samsung.com>2015-03-04 04:59:04 -0800
commit2e74a7b53c3c430da503bf1334dc057f9f03c299 (patch)
tree322cfbcdba86bf43adfa9e68ed6e0c6032669f14 /drivers/gpu/drm
parent00a9c3ed567d2e81316147eef8ad69e249dbedf6 (diff)
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drm/exynos: gsc: always use hw buffer 0 until queue management get fixed
Buffer sequence selection is broken and must be fixed. For the time being always queue buffers for hw id 0, because hardware always operates on the first src and dst buffer. This fixes IOMMU faults and makes the driver usable from userspace. Suggested-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Change-Id: I46f43a5ad8b714a78bad7383bc5e532bf5015ecd
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gsc.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 725e6587407..532508ec843 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -729,16 +729,16 @@ static int gsc_src_set_addr(struct device *dev,
switch (buf_type) {
case IPP_BUF_ENQUEUE:
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
- GSC_IN_BASE_ADDR_Y(buf_id));
+ GSC_IN_BASE_ADDR_Y(0));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
- GSC_IN_BASE_ADDR_CB(buf_id));
+ GSC_IN_BASE_ADDR_CB(0));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
- GSC_IN_BASE_ADDR_CR(buf_id));
+ GSC_IN_BASE_ADDR_CR(0));
break;
case IPP_BUF_DEQUEUE:
- gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
- gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
- gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_Y(0));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_CB(0));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_CR(0));
break;
default:
/* bypass */
@@ -1185,16 +1185,16 @@ static int gsc_dst_set_addr(struct device *dev,
switch (buf_type) {
case IPP_BUF_ENQUEUE:
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
- GSC_OUT_BASE_ADDR_Y(buf_id));
+ GSC_OUT_BASE_ADDR_Y(0));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
- GSC_OUT_BASE_ADDR_CB(buf_id));
+ GSC_OUT_BASE_ADDR_CB(0));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
- GSC_OUT_BASE_ADDR_CR(buf_id));
+ GSC_OUT_BASE_ADDR_CR(0));
break;
case IPP_BUF_DEQUEUE:
- gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
- gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
- gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(0));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(0));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(0));
break;
default:
/* bypass */