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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-01-31 13:51:20 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-02-20 16:00:46 +1000 |
| commit | 9bd2ddbaa241274cd11191838d080fc308ecf6c7 (patch) | |
| tree | 0e8ba52fb2034de4f3fcd977589e3a9bdad79b26 /drivers/gpu/drm/nouveau/core/include | |
| parent | 1d7c71a3e2f77336df536855b0efd2dc5bdeb41b (diff) | |
| download | linux-3.10-9bd2ddbaa241274cd11191838d080fc308ecf6c7.tar.gz linux-3.10-9bd2ddbaa241274cd11191838d080fc308ecf6c7.tar.bz2 linux-3.10-9bd2ddbaa241274cd11191838d080fc308ecf6c7.zip | |
drm/nouveau/fifo/nvc0-: use interrupt 31 as an event trigger
Generated if you try and use fifo method 0x20 on any subchannel, appears
that it can be safely masked off without stalling the whole GPU.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/include')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h index 543e4ef80f6..b46c197709f 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h @@ -65,6 +65,8 @@ struct nouveau_fifo_base { struct nouveau_fifo { struct nouveau_engine base; + struct nouveau_event *uevent; + struct nouveau_object **channel; spinlock_t lock; u16 min; |