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| author | Tomasz Figa <t.figa@samsung.com> | 2013-03-01 18:12:02 +0100 |
|---|---|---|
| committer | Chanho Park <chanho61.park@samsung.com> | 2014-11-18 11:42:37 +0900 |
| commit | 6be8ea5747ae5262801707832d606e00cb1b409d (patch) | |
| tree | ad761638fc501ea199a665b8dcfb9497fc659b2e /drivers/cpufreq | |
| parent | 9393ce09a96d8d2f26ae24c79f139534e9176dc5 (diff) | |
| download | linux-3.10-6be8ea5747ae5262801707832d606e00cb1b409d.tar.gz linux-3.10-6be8ea5747ae5262801707832d606e00cb1b409d.tar.bz2 linux-3.10-6be8ea5747ae5262801707832d606e00cb1b409d.zip | |
cpufreq: exynos4210: Use common clock operations for APLL configuration
This patch modifies the driver to use clk_set_rate for setting the rate
of APLL.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/cpufreq')
| -rw-r--r-- | drivers/cpufreq/exynos4210-cpufreq.c | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index 7e4c8862c03..05a2d67cf16 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -81,6 +81,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index) static void exynos4210_set_apll(unsigned int index) { + unsigned long freq = apll_freq_4210[index].freq * 1000; unsigned int tmp; /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ @@ -92,19 +93,7 @@ static void exynos4210_set_apll(unsigned int index) tmp &= 0x7; } while (tmp != 0x2); - /* 2. Set APLL Lock time */ - __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK); - - /* 3. Change PLL PMS values */ - tmp = __raw_readl(EXYNOS4_APLL_CON0); - tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); - tmp |= apll_freq_4210[index].mps; - __raw_writel(tmp, EXYNOS4_APLL_CON0); - - /* 4. wait_lock_time */ - do { - tmp = __raw_readl(EXYNOS4_APLL_CON0); - } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); + clk_set_rate(mout_apll, freq); /* 5. MUX_CORE_SEL = APLL */ clk_set_parent(moutcore, mout_apll); |