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authorTomasz Stanislawski <t.stanislaws@samsung.com>2013-10-07 14:27:52 +0200
committerChanho Park <chanho61.park@samsung.com>2014-11-18 11:46:58 +0900
commit0121bbac75ef2cfd421a9bde11d7b497a67e80f9 (patch)
tree3dd1119127d4622113c4872d8853d20436dbdae1 /drivers/clk
parentad309a5ba652c753aa1cdfbfb2e095a95d7883af (diff)
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clk: exynos4: export sclk_hdmiphy clock
Export sclk_hdmiphy clock to be usable from DT. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Change-Id: I0d1c8d0c2e2e93bd34f9fcdf82154208c2381a73
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index c0ee010c9e8..1a3fd05c352 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -143,7 +143,7 @@ enum exynos4_clks {
xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
- mout_apll, clkout, /* 21 */
+ mout_apll, clkout, sclk_hdmiphy, /* 22 */
/* gate for special clocks (sclk) */
sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
@@ -351,7 +351,7 @@ struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
/* fixed rate clocks generated inside the soc */
struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
- FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+ FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
};