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authorArnd Bergmann <arnd@arndb.de>2013-05-06 23:43:45 +0200
committerArnd Bergmann <arnd@arndb.de>2013-05-06 23:43:45 +0200
commit442a33ebce9e02a2dd6662f16c9f2aad834d0115 (patch)
treeca8654a286f61da917318645cab9e061095ecdba /drivers/clk/tegra/clk-periph-gate.c
parenta94d236dc355f374857ee4e6e78b7dec8a0f29e3 (diff)
parentf31c2f1c68aff83277eddc6798adf3438e9c680a (diff)
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Merge branch 'late/clksrc' into late/cleanup
There is no reason to keep the clksrc cleanups separate from the other cleanups, and this resolves some merge conflicts. Conflicts: arch/arm/mach-spear/spear13xx.c drivers/irqchip/Makefile
Diffstat (limited to 'drivers/clk/tegra/clk-periph-gate.c')
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7..bafee9895a2 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
#define write_rst_clr(val, gate) \
writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
-#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
+
+#define LVL2_CLK_GATE_OVRE 0x554
/* Peripheral gate clock ops */
static int clk_periph_is_enabled(struct clk_hw *hw)
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
}
}
+ if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
+ writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+ writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+ udelay(1);
+ writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+ }
+
spin_unlock_irqrestore(&periph_ref_lock, flags);
return 0;