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| author | Tomasz Figa <t.figa@samsung.com> | 2013-12-04 14:09:46 +0100 |
|---|---|---|
| committer | Marek Szyprowski <m.szyprowski@samsung.com> | 2014-05-15 07:25:43 +0200 |
| commit | 29fa37b2f8f95aa19e2fd662b7ddfda6011a22f4 (patch) | |
| tree | d2afada2d8679d70cf0c92e2169b378662f79d40 /drivers/clk/samsung/clk-exynos4.c | |
| parent | d37a08958ce87617704c438aa2560939fd0cc437 (diff) | |
| download | linux-3.10-29fa37b2f8f95aa19e2fd662b7ddfda6011a22f4.tar.gz linux-3.10-29fa37b2f8f95aa19e2fd662b7ddfda6011a22f4.tar.bz2 linux-3.10-29fa37b2f8f95aa19e2fd662b7ddfda6011a22f4.zip | |
clk: samsung: exynos4: Propagate rate change of SPI dividers
This patch adds missing CLK_SET_RATE_PARENT flag to div_spi{0,1,2} clocks
to allow rate change propagation to div_spi{0,1,2}_pre. This fixes the
problem with SPI bus clock rate setting.
Change-Id: I26ef7028297914d5c99e55f0e9fa6dc6a9292e94
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index b5ca0e24967..e7c4c59b3ec 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -534,11 +534,14 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), - DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), + DIV_F(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8, + CLK_SET_RATE_PARENT, 0), DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), - DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), + DIV_F(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8, + CLK_SET_RATE_PARENT, 0), DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), - DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), + DIV_F(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8, + CLK_SET_RATE_PARENT, 0), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), |