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| author | Tejun Heo <htejun@gmail.com> | 2007-10-16 14:21:24 -0700 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2007-10-29 06:15:27 -0400 |
| commit | 88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5 (patch) | |
| tree | ad6ab294a4f725540bfa24b7a451273b99fa71c1 /drivers/ata/pata_scc.c | |
| parent | 054a5fbaceb2eb3a31ea843c1cf0b8e10b91478c (diff) | |
| download | linux-3.10-88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5.tar.gz linux-3.10-88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5.tar.bz2 linux-3.10-88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5.zip | |
libata: implement ata_wait_after_reset()
On certain device/controller combination, 0xff status is asserted
after reset and doesn't get cleared during 150ms post-reset wait. As
0xff status is interpreted as no device (for good reasons), this can
lead to misdetection on such cases.
This patch implements ata_wait_after_reset() which replaces the 150ms
sleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff.
ATA_TMOUT_FF_WAIT is currently 800ms which is enough for
HHD424020F7SV00 to get detected but not enough for Quantum GoVault
drive which is known to take upto 2s.
Without parallel probing, spending 2s on 0xff port would incur too
much delay on ata_piix's which use 0xff to indicate empty port and
doesn't have SCR register, so GoVault needs to wait till parallel
probing.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_scc.c')
| -rw-r--r-- | drivers/ata/pata_scc.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c index 55576138fae..ea2ef9fc15b 100644 --- a/drivers/ata/pata_scc.c +++ b/drivers/ata/pata_scc.c @@ -570,17 +570,8 @@ static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask, udelay(20); out_be32(ioaddr->ctl_addr, ap->ctl); - /* spec mandates ">= 2ms" before checking status. - * We wait 150ms, because that was the magic delay used for - * ATAPI devices in Hale Landis's ATADRVR, for the period of time - * between when the ATA command register is written, and then - * status is checked. Because waiting for "a while" before - * checking status is fine, post SRST, we perform this magic - * delay here as well. - * - * Old drivers/ide uses the 2mS rule and then waits for ready - */ - msleep(150); + /* wait a while before checking status */ + ata_wait_after_reset(ap, deadline); /* Before we perform post reset processing we want to see if * the bus shows 0xFF because the odd clown forgets the D7 |