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author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2008-04-26 01:55:30 +0900 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:32 +0100 |
commit | 411ba7fcba54b30ba4ce2c492ea8d20f1d0db996 (patch) | |
tree | 1fe2b498d07cd685c142e037bda0885644f19705 /arch | |
parent | 855808392adf499a29e6bdb418f9474726ecbace (diff) | |
download | linux-3.10-411ba7fcba54b30ba4ce2c492ea8d20f1d0db996.tar.gz linux-3.10-411ba7fcba54b30ba4ce2c492ea8d20f1d0db996.tar.bz2 linux-3.10-411ba7fcba54b30ba4ce2c492ea8d20f1d0db996.zip |
[MIPS] Fix some sparse warnings on traps.c and irq-msc01.c
* Declare board_bind_eic_interrupt, board_watchpoint_handler in traps.h
* Make msc_bind_eic_interrupt static and fix its argument types.
* Make msc_levelirq_type, msc_edgeirq_type static.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 4edc7e451d9..963c16d266a 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/irq.h> #include <asm/msc01_ic.h> +#include <asm/traps.h> static unsigned long _icctrl_msc; #define MSC01_IC_REG_BASE _icctrl_msc @@ -98,14 +99,13 @@ void ll_msc_irq(void) } } -void -msc_bind_eic_interrupt(unsigned int irq, unsigned int set) +static void msc_bind_eic_interrupt(int irq, int set) { MSCIC_WRITE(MSC01_IC_RAMW, (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); } -struct irq_chip msc_levelirq_type = { +static struct irq_chip msc_levelirq_type = { .name = "SOC-it-Level", .ack = level_mask_and_ack_msc_irq, .mask = mask_msc_irq, @@ -115,7 +115,7 @@ struct irq_chip msc_levelirq_type = { .end = end_msc_irq, }; -struct irq_chip msc_edgeirq_type = { +static struct irq_chip msc_edgeirq_type = { .name = "SOC-it-Edge", .ack = edge_mask_and_ack_msc_irq, .mask = mask_msc_irq, @@ -128,8 +128,6 @@ struct irq_chip msc_edgeirq_type = { void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) { - extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); - _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000); /* Reset interrupt controller - initialises all registers to 0 */ |