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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-03-24 23:15:50 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:26 +0100 |
| commit | 0167509574ef1cdb516906db5e8b6ad5ca64ab61 (patch) | |
| tree | 3047fc8adf04601f529e2d497a36d1a79d4681bc /arch | |
| parent | a92b05880d261e9017ef8e7d5b6b01e0e5aa991d (diff) | |
| download | linux-3.10-0167509574ef1cdb516906db5e8b6ad5ca64ab61.tar.gz linux-3.10-0167509574ef1cdb516906db5e8b6ad5ca64ab61.tar.bz2 linux-3.10-0167509574ef1cdb516906db5e8b6ad5ca64ab61.zip | |
[MIPS] Alchemy: don't unmask timer IRQ early
Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:
- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
ALLINTS macro -- this change is blessed by AMD as I saw it in their own
patch; :-)
- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
no 32 KHz crystal.
Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/au1000/common/irq.c | 7 | ||||
| -rw-r--r-- | arch/mips/au1000/common/time.c | 8 |
2 files changed, 5 insertions, 10 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 3c7714f057a..5528e1412b5 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -1,7 +1,6 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. <source@mvista.com> * * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) * @@ -591,7 +590,7 @@ void __init arch_init_irq(void) imp++; } - set_c0_status(ALLINTS); + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); /* Board specific IRQ initialization. */ diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index e122bbc6cd8..1966964590a 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com + * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> * Copied and modified Carsten Langgaard's time.c * * Carsten Langgaard, carstenl@mips.com @@ -265,12 +265,8 @@ void __init plat_time_init(void) * Check to ensure we really have a 32KHz oscillator before * we do this. */ - if (no_au1xxx_32khz) { + if (no_au1xxx_32khz) printk("WARNING: no 32KHz clock found.\n"); - - /* Ensure we get CPO_COUNTER interrupts. */ - set_c0_status(IE_IRQ5); - } else { while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); au_writel(0, SYS_TOYWRITE); |