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| author | Dan Williams <dan.j.williams@intel.com> | 2008-11-06 17:43:55 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2008-11-06 10:48:29 -0700 |
| commit | c7cf72dcadbe39c2077b32460f86c9f8167be3be (patch) | |
| tree | 66984afe9b390596d1ae97e35aaeb4e6f52c412d /arch | |
| parent | 45beca08dd8b6d6a65c5ffd730af2eac7a2c7a03 (diff) | |
| download | linux-3.10-c7cf72dcadbe39c2077b32460f86c9f8167be3be.tar.gz linux-3.10-c7cf72dcadbe39c2077b32460f86c9f8167be3be.tar.bz2 linux-3.10-c7cf72dcadbe39c2077b32460f86c9f8167be3be.zip | |
[ARM] xsc3: fix xsc3_l2_inv_range
When 'start' and 'end' are less than a cacheline apart and 'start' is
unaligned we are done after cleaning and invalidating the first
cacheline. So check for (start < end) which will not walk off into
invalid address ranges when (start > end).
This issue was caught by drivers/dma/dmatest.
2.6.27 is susceptible.
Cc: <stable@kernel.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Cc: Lennert Buytenhek <buytenh@marvell.com>
Cc: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 10b1bae1a25..464de893a98 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -98,7 +98,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) /* * Clean and invalidate partial last cache line. */ - if (end & (CACHE_LINE_SIZE - 1)) { + if (start < end && (end & (CACHE_LINE_SIZE - 1))) { xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1)); xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); end &= ~(CACHE_LINE_SIZE - 1); @@ -107,7 +107,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) /* * Invalidate all full cache lines between 'start' and 'end'. */ - while (start != end) { + while (start < end) { xsc3_l2_inv_pa(start); start += CACHE_LINE_SIZE; } |