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| author | David Daney <ddaney@caviumnetworks.com> | 2009-05-12 12:41:54 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-17 11:06:26 +0100 |
| commit | 9e290a19f21f4d6c305090d3c61fbfad65908188 (patch) | |
| tree | 65a22ff83fb466cc3b8b639c660e7e05e16bc193 /arch | |
| parent | 41f0e4d041aa30507a34998c29d0b7ac0bede277 (diff) | |
| download | linux-3.10-9e290a19f21f4d6c305090d3c61fbfad65908188.tar.gz linux-3.10-9e290a19f21f4d6c305090d3c61fbfad65908188.tar.bz2 linux-3.10-9e290a19f21f4d6c305090d3c61fbfad65908188.zip | |
MIPS: Remove execution hazard barriers for Octeon.
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 04ce6e6569d..bb291f41b6a 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -47,6 +47,7 @@ #define cpu_has_mips32r2 0 #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 1 +#define cpu_has_mips_r2_exec_hazard 0 #define cpu_has_dsp 0 #define cpu_has_mipsmt 0 #define cpu_has_userlocal 0 |