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| author | Avinash H.M <avinashhm@ti.com> | 2011-05-09 12:29:40 +0000 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2011-05-13 07:08:18 -0700 |
| commit | 5fd2a84ab3c8b87176e25db1d98c5cc34043a669 (patch) | |
| tree | 8d876c82afc964481836e4a828b44958856c6252 /arch | |
| parent | c56b2ddd5ff4352cdb0df07eefba8068d043382e (diff) | |
| download | linux-3.10-5fd2a84ab3c8b87176e25db1d98c5cc34043a669.tar.gz linux-3.10-5fd2a84ab3c8b87176e25db1d98c5cc34043a669.tar.bz2 linux-3.10-5fd2a84ab3c8b87176e25db1d98c5cc34043a669.zip | |
OMAP3: set the core dpll clk rate in its set_rate function
The debug l3_ick/rate is not displaying the actual rate of the clock in
hardware. This is because, the core dpll set_rate function doesn't update the
clk.rate. After fixing, the l3_ick/rate is displaying proper values.
Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
Signed-off-by: Avinash.H.M <avinashhm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Wamsley <paul@pwsan.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37bb6b..d6e34dd9e7e 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); + clk->rate = rate; return 0; } |