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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-05 16:01:58 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-05 16:01:58 -0800 |
| commit | eb1c838fca2248ae62e5472b496ab52d3d774cc5 (patch) | |
| tree | dc1e70881e0048fc67131f009e25a1aaece60901 /arch | |
| parent | db677ffa5f5a4f15b9dad4d132b3477b80766d82 (diff) | |
| parent | e04ed38d4e0cd32141f723560efcc8252b0241e2 (diff) | |
| download | linux-3.10-eb1c838fca2248ae62e5472b496ab52d3d774cc5.tar.gz linux-3.10-eb1c838fca2248ae62e5472b496ab52d3d774cc5.tar.bz2 linux-3.10-eb1c838fca2248ae62e5472b496ab52d3d774cc5.zip | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6:
sparc64: Fix Niagara2 perf event handling.
sparc64: Fix NMI programming when perf events are active.
bbc_envctrl: Clean up properly if kthread_run() fails.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sparc/kernel/nmi.c | 3 | ||||
| -rw-r--r-- | arch/sparc/kernel/perf_event.c | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c index f30f4a1ead2..d242a734054 100644 --- a/arch/sparc/kernel/nmi.c +++ b/arch/sparc/kernel/nmi.c @@ -96,7 +96,6 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs) int cpu = smp_processor_id(); clear_softint(1 << irq); - pcr_ops->write(PCR_PIC_PRIV); local_cpu_data().__nmi_count++; @@ -105,6 +104,8 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs) if (notify_die(DIE_NMI, "nmi", regs, 0, pt_regs_trap_type(regs), SIGINT) == NOTIFY_STOP) touched = 1; + else + pcr_ops->write(PCR_PIC_PRIV); sum = kstat_irqs_cpu(0, cpu); if (__get_cpu_var(nmi_touch)) { diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index fa5936e1c3b..198fb4e79ba 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self, data.addr = 0; cpuc = &__get_cpu_var(cpu_hw_events); + + /* If the PMU has the TOE IRQ enable bits, we need to do a + * dummy write to the %pcr to clear the overflow bits and thus + * the interrupt. + * + * Do this before we peek at the counters to determine + * overflow so we don't lose any events. + */ + if (sparc_pmu->irq_bit) + pcr_ops->write(cpuc->pcr); + for (idx = 0; idx < MAX_HWEVENTS; idx++) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc; |