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| author | Dmitry Krivoschekov <dmitry.krivoschekov@gmail.com> | 2008-02-08 15:02:03 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-02-09 22:43:14 +0000 |
| commit | 86260f987319fb526e920fbe317933e5b3a0691e (patch) | |
| tree | 7ab271f7d98e79b368ec70744a5a20b896c38c8c /arch | |
| parent | f13fd3cc9147801bdf56f5964c58c9838a74dd47 (diff) | |
| download | linux-3.10-86260f987319fb526e920fbe317933e5b3a0691e.tar.gz linux-3.10-86260f987319fb526e920fbe317933e5b3a0691e.tar.bz2 linux-3.10-86260f987319fb526e920fbe317933e5b3a0691e.zip | |
[ARM] 4824/1: pxa: clear RDH bit after any reset
According to PXA300/310 and PXA320 Developer manuals,
the ASCR[RDH] "bit needs to be cleared as part of the software
initialization coming out of any reset and coming out of D3".
The latter requirement is addressed by commit
"c4d1fb627ff3072", as for the former (coming out of any reset),
the kernel relies on boot loaders and assumes that RDH bit
is cleared there. Though, not all bootloaders follow the rule
so we have to clear the bit in kernel.
We clear the RDH bit in pxa3xx_init() function since
it is always invoked after any reset. We also preserve D1S, D2S
and D3S bits from being cleared in case we invoke pxa3xx_init()
function not from normal hardware reset (e.g. kexec scenario),
so these bits can be properly referenced later.
Signed-off-by: Dmitry Krivoschekov <dmitry.krivoschekov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-pxa/pxa3xx.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 4b048b1e805..7cd9ef8deb0 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -513,6 +513,14 @@ static int __init pxa3xx_init(void) int i, ret = 0; if (cpu_is_pxa3xx()) { + /* + * clear RDH bit every time after reset + * + * Note: the last 3 bits DxS are write-1-to-clear so carefully + * preserve them here in case they will be referenced later + */ + ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); if ((ret = pxa_init_dma(32))) |