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| author | Eric Miao <ycmiao@ycmiao-hp520.(none)> | 2008-12-17 16:50:43 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@marvell.com> | 2008-12-29 17:59:17 +0800 |
| commit | 6e354846e807e037751fdc8faaee8ad492177113 (patch) | |
| tree | eb31ad176a03091ff02560d2623ed9952fa19dc6 /arch | |
| parent | 7e4b19c95c8632b543bd510ec6c710bebb53b840 (diff) | |
| download | linux-3.10-6e354846e807e037751fdc8faaee8ad492177113.tar.gz linux-3.10-6e354846e807e037751fdc8faaee8ad492177113.tar.bz2 linux-3.10-6e354846e807e037751fdc8faaee8ad492177113.zip | |
[ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching
dma branching is enabled by extending the current setup_frame_dma()
function to allow a 2nd set of frame/palette dma descriptors to be
used.
As a result, pxafb_dma_buff.dma_desc[], pxafb_dma_buff.pal_desc[]
and pxafb_info.fdadr[] are doubled.
This allows maximum re-use of the current dma setup code, although
the pxafb_info.fdadr[xx] for FBRx register values looks a bit odd.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Eric Miao <ycmiao@ycmiao-hp520.(none)>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-lcd.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index f817878d256..c15df557fa8 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h @@ -12,13 +12,19 @@ #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ -#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ #define LCSR (0x038) /* LCD Controller Status Register */ #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ #define TMEDCR (0x044) /* TMED Control Register */ +#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ +#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ +#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ +#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ + #define CMDCR (0x100) /* Command Control Register */ #define PRSR (0x104) /* Panel Read Status Register */ |