path: root/arch
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authorTushar Behera <>2014-07-07 23:31:41 (GMT)
committerHyungwon Hwang <>2014-12-17 07:18:11 (GMT)
commitf92537178cfafeaca6f2f7b68a7fea6549eb1c1a (patch)
treeee5574cc70524513ef26a733c4a28edc95f94df4 /arch
parent7695aa70e41dc5b6535fc3bec3e756365e5d07a3 (diff)
ARM: dts: Update the parent for Audss clocks in Exynos5420
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by: Tushar Behera <> Signed-off-by: Shaik Ameer Basha <> Reported-by: Kevin Hilman <> Tested-by: Javier Martinez Canillas <> Tested-by: Doug Anderson <> Signed-off-by: Kukjin Kim <>
Diffstat (limited to 'arch')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..79e9119 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";