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authorChanho Park <chanho61.park@samsung.com>2015-01-05 04:52:09 (GMT)
committerChanho Park <chanho61.park@samsung.com>2015-01-05 04:53:10 (GMT)
commit62fd724163d57c4809d424926c146da145239874 (patch)
tree10e297daa58edf079715e7b1a3053b4483dbf4bb /arch
parentfe6794c2207cf1a5b687e82d4088625d11401fe3 (diff)
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Revert "ARM: exynos: add support secondary core bootup in big.LITTLE processor."refs/changes/65/33065/1
This reverts commit c25aae8a02c0e3132df581d1d12be1d6738a08d6. I think we need to investigate this patch more and more. Change-Id: Idb69b33334f53ddd414123f6e9ac432840b99857 Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos/headsmp.S2
-rw-r--r--arch/arm/mach-exynos/hotplug.c7
-rw-r--r--arch/arm/mach-exynos/platsmp.c32
3 files changed, 15 insertions, 26 deletions
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index b124366..5364d4b 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -22,7 +22,7 @@
*/
ENTRY(exynos4_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #0xFFFFFF
+ and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 44932a8..4c97426 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -94,13 +94,10 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
u32 mpidr = cpu_logical_map(cpu);
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- u32 cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- cluster_id = cluster_id > 1 ? 0 : cluster_id;
- u32 cpu_idx = (cluster_id * 4) + core_id;
for (;;) {
/* Turn the CPU off on next WFI instruction. */
- exynos_cpu_power_down(cpu_idx);
+ exynos_cpu_power_down(core_id);
/*
* here's the WFI
@@ -110,7 +107,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
:
: "memory", "cc");
- if (pen_release == cpu_idx) {
+ if (pen_release == core_id) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8deffeb..9a8d557 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -95,9 +95,6 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
unsigned long timeout;
u32 mpidr = cpu_logical_map(cpu);
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- u32 cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- cluster_id = cluster_id > 1 ? 0 : cluster_id;
- u32 cpu_idx = (cluster_id * 4) + core_id;
/*
* Set synchronisation state between this boot processor
@@ -113,21 +110,21 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
* Note that "pen_release" is the hardware CPU core ID, whereas
* "cpu" is Linux's internal ID.
*/
- write_pen_release(mpidr);
+ write_pen_release(core_id);
- if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpu_idx))
+ if (!(__raw_readl(S5P_ARM_CORE_STATUS(core_id))
& S5P_CORE_LOCAL_PWR_EN)) {
u32 core_conf = 0;
core_conf |= S5P_CORE_LOCAL_PWR_EN;
if (soc_is_exynos3250())
core_conf |= S5P_CORE_AUTOWAKEUP_EN;
- __raw_writel(core_conf, S5P_ARM_CORE_CONFIGURATION(cpu_idx));
+ __raw_writel(core_conf, S5P_ARM_CORE_CONFIGURATION(core_id));
timeout = 10;
/* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE_STATUS(cpu_idx))
+ while ((__raw_readl(S5P_ARM_CORE_STATUS(core_id))
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -151,13 +148,13 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
udelay(10);
udelay(10);
- tmp = __raw_readl(S5P_ARM_CORE_STATUS(cpu_idx));
+ tmp = __raw_readl(S5P_ARM_CORE_STATUS(core_id));
tmp |= (S5P_CORE_LOCAL_PWR_EN << 8);
- __raw_writel(tmp, S5P_ARM_CORE_STATUS(cpu_idx));
+ __raw_writel(tmp, S5P_ARM_CORE_STATUS(core_id));
}
if (soc_is_exynos3250())
- __raw_writel(EXYNOS3_COREPORESET(cpu_idx), EXYNOS_SWRESET);
+ __raw_writel(EXYNOS3_COREPORESET(core_id), EXYNOS_SWRESET);
/*
* Send the secondary CPU a soft interrupt, thereby causing
@@ -177,10 +174,10 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
* Try to set boot address using firmware first
* and fall back to boot register if it fails.
*/
- if (call_firmware_op(set_cpu_boot_addr, cpu_idx, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(cpu_idx));
+ if (call_firmware_op(set_cpu_boot_addr, core_id, boot_addr))
+ __raw_writel(boot_addr, cpu_boot_reg(core_id));
- call_firmware_op(cpu_boot, cpu_idx);
+ call_firmware_op(cpu_boot, core_id);
if (soc_is_exynos3250())
dsb_sev();
@@ -248,18 +245,13 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
unsigned long boot_addr;
u32 mpidr;
u32 core_id;
- u32 cluster_id;
- u32 cpu_idx;
mpidr = cpu_logical_map(i);
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- cluster_id = cluster_id > 1 ? 0 : cluster_id;
- cpu_idx = (cluster_id * 4) + core_id;
boot_addr = virt_to_phys(exynos4_secondary_startup);
- if (call_firmware_op(set_cpu_boot_addr, cpu_idx, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(cpu_idx));
+ if (call_firmware_op(set_cpu_boot_addr, core_id, boot_addr))
+ __raw_writel(boot_addr, cpu_boot_reg(core_id));
}
}