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| author | Vince Weaver <vincent.weaver@maine.edu> | 2012-10-19 17:30:01 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2012-10-24 10:31:57 +0200 |
| commit | 7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a (patch) | |
| tree | 24ecd56e9039b7f990f4b6d0da1f2ddbc009279e /arch/x86 | |
| parent | c13d38e4a1fd5dd07135403c613c8091af444169 (diff) | |
| download | linux-3.10-7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a.tar.gz linux-3.10-7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a.tar.bz2 linux-3.10-7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a.zip | |
perf/x86: Fix P6 FP_ASSIST event constraint
According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only,
not Counter 0.
Tested on a Pentium II.
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191728570.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_p6.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index e4dd0f7a045..0ff5f7fb64c 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c @@ -34,7 +34,7 @@ static struct event_constraint p6_event_constraints[] = { INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ - INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */ + INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ |