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| author | Paul Mundt <lethal@linux-sh.org> | 2007-07-06 10:58:04 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-07-06 10:58:04 +0900 |
| commit | 04c7d9579f25ff0dd01efa958805f34c92bc6a71 (patch) | |
| tree | 125a0da3b1d4397af86b562c5b4e8df1eedf10ab /arch/sh/lib | |
| parent | 75f016a7ce75220d898608791870ab7da549a430 (diff) | |
| download | linux-3.10-04c7d9579f25ff0dd01efa958805f34c92bc6a71.tar.gz linux-3.10-04c7d9579f25ff0dd01efa958805f34c92bc6a71.tar.bz2 linux-3.10-04c7d9579f25ff0dd01efa958805f34c92bc6a71.zip | |
sh: Correct __xdiv64_32/div64_32 return value size.
These should be returning a uint32_t, whereas they were erroneously
returning a u64 before. As the register sizes are 32-bits, this doesn't
really make a lot of sense.
Reported-by: Katsuya MATSUBARA <matsu@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/lib')
| -rw-r--r-- | arch/sh/lib/div64-generic.c | 9 | ||||
| -rw-r--r-- | arch/sh/lib/div64.S | 6 |
2 files changed, 7 insertions, 8 deletions
diff --git a/arch/sh/lib/div64-generic.c b/arch/sh/lib/div64-generic.c index c02473afd58..d9482cd2a9e 100644 --- a/arch/sh/lib/div64-generic.c +++ b/arch/sh/lib/div64-generic.c @@ -4,16 +4,15 @@ #include <linux/types.h> -extern u64 __xdiv64_32(u64 n, u32 d); +extern uint32_t __xdiv64_32(u64 n, u32 d); -u64 __div64_32(u64 *xp, u32 y) +uint32_t __div64_32(u64 *xp, u32 y) { - u64 rem; - u64 q = __xdiv64_32(*xp, y); + uint32_t rem; + uint32_t q = __xdiv64_32(*xp, y); rem = *xp - q * y; *xp = q; return rem; } - diff --git a/arch/sh/lib/div64.S b/arch/sh/lib/div64.S index eefc275d64a..5ee7334ea64 100644 --- a/arch/sh/lib/div64.S +++ b/arch/sh/lib/div64.S @@ -1,12 +1,12 @@ /* - * unsigned long long __xdiv64_32(unsigned long long n, unsigned long d); + * unsigned long __xdiv64_32(unsigned long long n, unsigned long d); */ #include <linux/linkage.h> .text ENTRY(__xdiv64_32) -#ifdef __LITTLE_ENDIAN__ +#ifdef CONFIG_CPU_LITTLE_ENDIAN mov r4, r0 mov r5, r1 #else @@ -34,7 +34,7 @@ ENTRY(__xdiv64_32) rotcl r0 div1 r6, r1 .endr -#ifdef __LITTLE_ENDIAN__ +#ifdef CONFIG_CPU_LITTLE_ENDIAN mov r2, r1 rts rotcl r0 |