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| author | David Daney <ddaney@caviumnetworks.com> | 2010-02-10 15:12:48 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 12:53:26 +0100 |
| commit | 6f329468f3086e9d8f3832930fdb09ab3769176b (patch) | |
| tree | d77b274399cf101fba59b0de01fd9491b4e28fee /arch/mips | |
| parent | 6dd9344cfc41bcc60a01cdc828cb278be7a10e01 (diff) | |
| download | linux-3.10-6f329468f3086e9d8f3832930fdb09ab3769176b.tar.gz linux-3.10-6f329468f3086e9d8f3832930fdb09ab3769176b.tar.bz2 linux-3.10-6f329468f3086e9d8f3832930fdb09ab3769176b.zip | |
MIPS: Give Octeon+ CPUs their own cputype.
This allows us to treat them differently at runtime.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 9 | ||||
| -rw-r--r-- | arch/mips/mm/c-octeon.c | 7 |
3 files changed, 12 insertions, 6 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index cf373a95fe4..a5acda41694 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -224,7 +224,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9ea5ca89e85..be5bb16be4e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -162,6 +162,7 @@ void __init check_wait(void) case CPU_BCM6348: case CPU_BCM6358: case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: cpu_wait = r4k_wait; break; @@ -911,12 +912,16 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: + c->cputype = CPU_CAVIUM_OCTEON; + __cpu_name[cpu] = "Cavium Octeon"; + goto platform; case PRID_IMP_CAVIUM_CN58XX: case PRID_IMP_CAVIUM_CN56XX: case PRID_IMP_CAVIUM_CN50XX: case PRID_IMP_CAVIUM_CN52XX: - c->cputype = CPU_CAVIUM_OCTEON; - __cpu_name[cpu] = "Cavium Octeon"; + c->cputype = CPU_CAVIUM_OCTEON_PLUS; + __cpu_name[cpu] = "Cavium Octeon+"; +platform: if (cpu == 0) __elf_platform = "octeon"; break; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index af85959e59f..0f9c488044d 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; |