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authorRalf Baechle <ralf@linux-mips.org>2013-03-12 16:06:07 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-03-12 18:58:09 +0100
commitf4cdb6a00c148e7724ada0998643b293a52b5f62 (patch)
tree69d7d9ccfca7d8f9fee2effd69a0b2ae055b3b2f /arch/mips
parent631b0af98c1efb160f02154743ae9f13fe03e347 (diff)
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MIPS: SEAD3: Enable LL/SC.
All synthesizable CPU cores that could be loaded into a SEAD3's FPGA are MIPS32 or MIPS64 CPUs that have ll/sc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index b40f37fb3de..193c0912d38 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,7 +28,7 @@
/* #define cpu_has_prefetch ? */
#define cpu_has_mcheck 1
/* #define cpu_has_ejtag ? */
-#define cpu_has_llsc 0
+#define cpu_has_llsc 1
/* #define cpu_has_vtag_icache ? */
/* #define cpu_has_dc_aliases ? */
/* #define cpu_has_ic_fills_f_dc ? */