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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-03-14 10:45:19 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-15 17:49:07 +0200 |
| commit | 703327ddcc736a054f4e2c132235a8370d2f7870 (patch) | |
| tree | 2c7f616a4bbb04eeb55a5895f8e9da99ba357606 /arch/mips/include/asm | |
| parent | e9b62e8ef9d71ed977797529fc0dfc352448d50b (diff) | |
| download | linux-3.10-703327ddcc736a054f4e2c132235a8370d2f7870.tar.gz linux-3.10-703327ddcc736a054f4e2c132235a8370d2f7870.tar.bz2 linux-3.10-703327ddcc736a054f4e2c132235a8370d2f7870.zip | |
MIPS: ath79: add early_printk support for AR934X
The patch allows to see kernel messages on AR934X SoCs in
early boot stage.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3504/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 2f0becb4ec8..b7df6749479 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -1,10 +1,11 @@ /* * Atheros AR71XX/AR724X/AR913X SoC register definitions * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -249,6 +250,9 @@ #define REV_ID_MAJOR_AR7242 0x1100 #define REV_ID_MAJOR_AR9330 0x0110 #define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 |