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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-16 11:11:31 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-16 11:11:31 -0700
commitd34e14f690d611ffe3db09e4ed8123d86c89a831 (patch)
treedc7d6716e2550834816e29e5928a60c00c97d9fc /arch/mips/include/asm/mipsregs.h
parent18e41da89d55014d25b9a24502ee92b7f50599f9 (diff)
parent4e73238d163c6fcf001264832701d2a6d4927672 (diff)
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: MIPS: Oprofile: Fix Loongson irq handler MIPS: N32: Use compat version for sys_ppoll. MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
-rw-r--r--arch/mips/include/asm/mipsregs.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 49382d5e891..c6e3c93ce7c 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -135,6 +135,12 @@
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
/*
+ * Bits 18 - 20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD 0x001c0000
+
+/*
* X the exception cause indicator
* E the exception enable
* S the sticky/flag bit
@@ -161,7 +167,8 @@
#define FPU_CSR_UDF_S 0x00000008
#define FPU_CSR_INE_S 0x00000004
-/* rounding mode */
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM 0x00000003
#define FPU_CSR_RN 0x0 /* nearest */
#define FPU_CSR_RZ 0x1 /* towards zero */
#define FPU_CSR_RU 0x2 /* towards +Infinity */