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| author | John A. Williams <john.williams@petalogix.com> | 2011-05-24 18:57:11 +1000 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2011-07-25 09:13:42 +0200 |
| commit | 8904976e8ca45be3ec75acc71f5d855ef671a079 (patch) | |
| tree | 9c76c35266329312ace36ab009d686d5e2cd77f8 /arch/microblaze/include | |
| parent | 5db34eb92f5699361de355dcd7958fdd2a9fb98a (diff) | |
| download | linux-3.10-8904976e8ca45be3ec75acc71f5d855ef671a079.tar.gz linux-3.10-8904976e8ca45be3ec75acc71f5d855ef671a079.tar.bz2 linux-3.10-8904976e8ca45be3ec75acc71f5d855ef671a079.zip | |
microblaze: Unprivileged stream instruction awareness
Add cpuinfo support for the new MicroBlaze option permitting userspace
(unprivileged) access to the streaming instructions (FSL / AXI-stream).
Emit a noisy warning at bootup if this is enabled, because bad user code
can potentially lockup the CPU.
Signed-off-by: John A. Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/include')
| -rw-r--r-- | arch/microblaze/include/asm/cpuinfo.h | 1 | ||||
| -rw-r--r-- | arch/microblaze/include/asm/pvr.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h index d8f013347a9..7d6831ac8a4 100644 --- a/arch/microblaze/include/asm/cpuinfo.h +++ b/arch/microblaze/include/asm/cpuinfo.h @@ -38,6 +38,7 @@ struct cpuinfo { u32 use_exc; u32 ver_code; u32 mmu; + u32 mmu_privins; u32 endian; /* CPU caches */ diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h index 56a80e45c4e..4bbdb4c03b5 100644 --- a/arch/microblaze/include/asm/pvr.h +++ b/arch/microblaze/include/asm/pvr.h @@ -117,10 +117,10 @@ struct pvr_s { #define PVR11_MMU_DTLB_SIZE 0x07000000 #define PVR11_MMU_TLB_ACCESS 0x00C00000 #define PVR11_MMU_ZONES 0x003C0000 +#define PVR11_MMU_PRIVINS 0x00010000 /* MSR Reset value PVR mask */ #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF - /* PVR access macros */ #define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK) #define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK) @@ -216,6 +216,7 @@ struct pvr_s { #define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) #define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) #define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES) +#define PVR_MMU_PRIVINS(pvr) (pvr.pvr[11] & PVR11_MMU_PRIVINS) /* endian */ #define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI) |