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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 13:35:55 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:18 +1000 |
| commit | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (patch) | |
| tree | d478523ee8bec4ecc638c9f9a35816fc12aaa37f /arch/m68k/include/asm/m52xxacr.h | |
| parent | 3d461401eb5e3a8c471e92500aebd6c115273fba (diff) | |
| download | linux-3.10-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.gz linux-3.10-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.bz2 linux-3.10-8ce877a8eb8293b5b2c07f259d694026b0f519e4.zip | |
m68knommu: clean up ColdFire cache control code
The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m52xxacr.h')
| -rw-r--r-- | arch/m68k/include/asm/m52xxacr.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 4c92d999ee0..52230b5e1e4 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -52,5 +52,32 @@ #define ACR_BWE 0x00000020 /* Write buffer enabled */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This code is set to + * only use the instruction cache, even on the controllers that support + * split cache. (This setup is trying to preserve the existing behavior + * for now, in the furture I hope to actually use the split cache mode). + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5249) || defined(CONFIG_M5272) +#define CACHE_INIT (CACR_CINV) +#define CACHE_MODE (CACR_CENB + CACR_DCM) +#else +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_INIT (CACR_CINV + CACR_DISD) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) +#else +#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) +#endif +#endif + +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m52xxsim_h */ |