diff options
| author | Christoph Lameter <clameter@sgi.com> | 2007-08-01 12:37:17 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-08-01 13:15:14 -0700 |
| commit | 40d485753423b87239cc16b6c8141ef8792324d9 (patch) | |
| tree | d2d4413d4520f6cde5908b966ab6f572069fc0c1 /arch/ia64 | |
| parent | 224685c0d1ca5970364c9f5d4f21ea1aa64c381e (diff) | |
| download | linux-3.10-40d485753423b87239cc16b6c8141ef8792324d9.tar.gz linux-3.10-40d485753423b87239cc16b6c8141ef8792324d9.tar.bz2 linux-3.10-40d485753423b87239cc16b6c8141ef8792324d9.zip | |
[IA64] SN2: Fix up sn2_rtc clock
If the sn2_rtc clock is present then it is a must have since sn2_rtc
provides a synchronized time source on Altix systems. So elevate
the priority to 450. Otherwise the ITC would take precendence. Altix
systems currently do not boot because the ITC clocksource is broken. It
seems to assume that ITCs are synchronized and as a result nanosleep
hangs (may be fixed in a different patch).
While we are at it: Remove the sn2_mc definition. The sn2_rtc has a fixed
address. No point in reading the address from memory. Removing it avoids
touching one cacheline.
Signed-off-by: Christoph Lameter <clameter@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
| -rw-r--r-- | arch/ia64/sn/kernel/sn2/timer.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/ia64/sn/kernel/sn2/timer.c b/arch/ia64/sn/kernel/sn2/timer.c index 19e25d2b64f..cf67fc56205 100644 --- a/arch/ia64/sn/kernel/sn2/timer.c +++ b/arch/ia64/sn/kernel/sn2/timer.c @@ -23,16 +23,14 @@ extern unsigned long sn_rtc_cycles_per_second; -static void __iomem *sn2_mc; - static cycle_t read_sn2(void) { - return (cycle_t)readq(sn2_mc); + return (cycle_t)readq(RTC_COUNTER_ADDR); } static struct clocksource clocksource_sn2 = { .name = "sn2_rtc", - .rating = 300, + .rating = 450, .read = read_sn2, .mask = (1LL << 55) - 1, .mult = 0, @@ -58,7 +56,6 @@ ia64_sn_udelay (unsigned long usecs) void __init sn_timer_init(void) { - sn2_mc = RTC_COUNTER_ADDR; clocksource_sn2.fsys_mmio = RTC_COUNTER_ADDR; clocksource_sn2.mult = clocksource_hz2mult(sn_rtc_cycles_per_second, clocksource_sn2.shift); |