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| author | Haojian Zhuang <haojian.zhuang@marvell.com> | 2009-08-19 19:30:24 +0800 |
|---|---|---|
| committer | Eric Miao <eric.y.miao@gmail.com> | 2009-09-10 18:49:26 +0800 |
| commit | 6ba39282bb3ee486a142ee3fd61196d329622ed9 (patch) | |
| tree | ee1efaebdd04489ec844a478d2d713bfc88b96bb /arch/arm | |
| parent | 4646dd2795e793f97b7fd40206567bf72e6cdf21 (diff) | |
| download | linux-3.10-6ba39282bb3ee486a142ee3fd61196d329622ed9.tar.gz linux-3.10-6ba39282bb3ee486a142ee3fd61196d329622ed9.tar.bz2 linux-3.10-6ba39282bb3ee486a142ee3fd61196d329622ed9.zip | |
[ARM] pxa: add more registers in interrupt controller
Add priority registers and new registers of pxa935.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-intc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h index ad23e74b762..68464ce1c1e 100644 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h @@ -13,6 +13,7 @@ #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ @@ -20,4 +21,14 @@ #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ +#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */ +#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */ +#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */ +#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ +#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ + +#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ + : (x < 64 ? (0x94 + ((x - 32) << 2)) \ + : (0x128 + ((x - 64) << 2))))) + #endif /* __ASM_MACH_REGS_INTC_H */ |