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| author | Andrew Bresticker <abrestic@chromium.org> | 2014-05-16 04:23:26 +0900 |
|---|---|---|
| committer | Hyungwon Hwang <human.hwang@samsung.com> | 2014-12-17 16:18:10 +0900 |
| commit | bbd865031f2076409e7fc5ebd7839d38ee3af8d9 (patch) | |
| tree | 532f6bdcf8d946da01c06f9a85f3d3e1160fb1e8 /arch/arm | |
| parent | 69ce8909a88661e405f5521c749ab15aab8fbc61 (diff) | |
| download | linux-3.10-bbd865031f2076409e7fc5ebd7839d38ee3af8d9.tar.gz linux-3.10-bbd865031f2076409e7fc5ebd7839d38ee3af8d9.tar.bz2 linux-3.10-bbd865031f2076409e7fc5ebd7839d38ee3af8d9.zip | |
ARM: dts: add CCI node for exynos5420
Add device-tree bindings for the ARM CCI-400 on Exynos5420. There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 1e886f3bc10..638efd5a845 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -58,6 +58,7 @@ compatible = "arm,cortex-a15"; reg = <0x0>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { @@ -65,6 +66,7 @@ compatible = "arm,cortex-a15"; reg = <0x1>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu2: cpu@2 { @@ -72,6 +74,7 @@ compatible = "arm,cortex-a15"; reg = <0x2>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu3: cpu@3 { @@ -79,6 +82,7 @@ compatible = "arm,cortex-a15"; reg = <0x3>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu4: cpu@100 { @@ -86,6 +90,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu5: cpu@101 { @@ -93,6 +98,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu6: cpu@102 { @@ -100,6 +106,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu7: cpu@103 { @@ -107,6 +114,26 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + }; + }; + + cci@10d20000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10d20000 0x1000>; + ranges = <0x0 0x10d20000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; }; }; |