Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
  [ARM] spelling fixes
  [ARM] at91_adc parenthesis balance
  [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition
  [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings
  [ARM] 4398/1: S3C2443: Fix watchdog IRQ number
  [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity
  [ARM] 4396/1: S3C2443: Add missing HCLK clocks
  [ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines
  [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu
  [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts
  [ARM] ARMv6: add CPU_HAS_ASID configuration
  [ARM] integrator: fix pci_v3 compile error with DEBUG_LL
  [ARM] gic: Fix gic cascade irq handling
  [ARM] Silence OMAP kernel configuration warning
  [ARM] Update ARM syscalls
  [ARM] 4384/1: S3C2412/13 SPI registers offset correction
  [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
  [ARM] 4382/1: iop13xx: fix msi support
  [ARM] Remove Integrator/CP SMP platform support
  [ARM] 4378/1: KS8695: Serial driver fix
  ...

4 files changed, 11 insertions, 3 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 15f0284010c..5f472a8b406 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -351,6 +351,7 @@ config CPU_V6
 	select CPU_CACHE_V6
 	select CPU_CACHE_VIPT
 	select CPU_CP15_MMU
+	select CPU_HAS_ASID
 	select CPU_COPY_V6 if MMU
 	select CPU_TLB_V6 if MMU
 
@@ -376,6 +377,7 @@ config CPU_V7
 	select CPU_CACHE_V7
 	select CPU_CACHE_VIPT
 	select CPU_CP15_MMU
+	select CPU_HAS_ASID
 	select CPU_COPY_V6 if MMU
 	select CPU_TLB_V6 if MMU
 
@@ -498,6 +500,12 @@ config CPU_TLB_V6
 
 endif
 
+config CPU_HAS_ASID
+	bool
+	help
+	  This indicates whether the CPU has the ASID register; used to
+	  tag TLB and possibly cache entries.
+
 config CPU_CP15
 	bool
 	help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 19ca333240e..36440c89958 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 1995  Linus Torvalds
  *  Modifications for ARM processor (c) 1995-2001 Russell King
- *  Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
+ *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
  *
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index d6167ad4e01..f3ade18862a 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr)
 #ifndef CONFIG_SMP
 	/*
 	 * If this is a section based mapping we need to handle it
-	 * specially as the VM subysystem does not know how to handle
+	 * specially as the VM subsystem does not know how to handle
 	 * such a beast. We need the lock here b/c we need to clear
 	 * all the mappings before the area can be reclaimed
 	 * by someone else.
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2ba1530d1ce..02e050ae59f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = {
 };
 
 /*
- * These are useful for identifing cache coherency
+ * These are useful for identifying cache coherency
  * problems by allowing the cache or the cache and
  * writebuffer to be turned off.  (Note: the write
  * buffer should not be on and the cache off).