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| author | Simon Horman <horms@verge.net.au> | 2012-09-28 02:12:45 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-10-21 09:27:58 -0700 |
| commit | 90e4ed1b7de612e4ed18029e61134ab2fea6233e (patch) | |
| tree | 3e796aa4bb46f3f647b19685305a99fdae7e566c /arch/arm/mm | |
| parent | 023f18fee60cd9ef86c8299dd9debccad1f93351 (diff) | |
| download | linux-3.10-90e4ed1b7de612e4ed18029e61134ab2fea6233e.tar.gz linux-3.10-90e4ed1b7de612e4ed18029e61134ab2fea6233e.tar.bz2 linux-3.10-90e4ed1b7de612e4ed18029e61134ab2fea6233e.zip | |
ARM: 7541/1: Add ARM ERRATA 775420 workaround
commit 7253b85cc62d6ff84143d96fe6cd54f73736f4d7 upstream.
arm: Add ARM ERRATA 775420 workaround
Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.
Based on work by Kouei Abe and feedback from Catalin Marinas.
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
[ horms@verge.net.au: Changed to implementation
suggested by catalin.marinas@arm.com ]
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a655d3da386..82ab2c5b4ac 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range) * isn't mapped, just try the next page. */ 9001: +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif mov r12, r12, lsr #12 mov r12, r12, lsl #12 add r12, r12, #4096 |