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| author | Catalin Marinas <catalin.marinas@arm.com> | 2012-06-25 14:59:38 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-07-09 17:39:38 +0100 |
| commit | 9ad86ddde0345e903eb74837e52cf19fe0c7f825 (patch) | |
| tree | 15d6bbaa38a0c7e4b55b4ee65edfa465e876efb4 /arch/arm/mm/mmu.c | |
| parent | 02df19b4227e5b799e4642e88b568f9474fa78d0 (diff) | |
| download | linux-3.10-9ad86ddde0345e903eb74837e52cf19fe0c7f825.tar.gz linux-3.10-9ad86ddde0345e903eb74837e52cf19fe0c7f825.tar.bz2 linux-3.10-9ad86ddde0345e903eb74837e52cf19fe0c7f825.zip | |
ARM: 7436/1: Do not map the vectors page as write-through on UP systems
The vectors page has been traditionally mapped as WT on UP systems but
this creates a mismatched alias with the directly mapped RAM that is
using WB attributes. On newer processors like Cortex-A15 this has
implications on the data/instructions coherency at the point of
unification (usually L2).
This patch removes such restriction.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/mmu.c')
| -rw-r--r-- | arch/arm/mm/mmu.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e5dad60b558..f37dc1856a6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -422,12 +422,6 @@ static void __init build_mem_type_table(void) vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; /* - * Only use write-through for non-SMP systems - */ - if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) - vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; - - /* * Enable CPU-specific coherency if supported. * (Only available on XSC3 at the moment.) */ |