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| author | Yauhen Kharuzhy <jekhor@gmail.com> | 2009-08-19 16:31:03 +0300 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-10 11:44:03 +0900 |
| commit | 7cfdee9f6791fe9ec288e75ee746790ebf3b6c3b (patch) | |
| tree | 4a2452f8359e0894f2c67689bc938fc4b8b316b1 /arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h | |
| parent | 4fcfce9f33cd2e173f83c20e93c8b0a9397bf0bc (diff) | |
| download | linux-3.10-7cfdee9f6791fe9ec288e75ee746790ebf3b6c3b.tar.gz linux-3.10-7cfdee9f6791fe9ec288e75ee746790ebf3b6c3b.tar.bz2 linux-3.10-7cfdee9f6791fe9ec288e75ee746790ebf3b6c3b.zip | |
ARM: S3C2416: Add S3C2416-specific registers definitions
Add macros for S3C2416 SoC support.
Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
[ben-linux@fluff.org: removed files that need changing]
[ben-linux@fluff.org: Fix S3C2416_GPH0_TXD0 definition]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h new file mode 100644 index 00000000000..2f31b74974a --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h @@ -0,0 +1,30 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h + * + * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, + * as part of OpenInkpot project + * Copyright (c) 2009 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2416 memory register definitions +*/ + +#ifndef __ASM_ARM_REGS_S3C2416_MEM +#define __ASM_ARM_REGS_S3C2416_MEM + +#ifndef S3C2416_MEMREG +#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) +#endif + +#define S3C2416_BANKCFG S3C2416_MEMREG(0x00) +#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04) +#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08) +#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C) + +#define S3C2416_REFRESH S3C2416_MEMREG(0x10) +#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14) + +#endif /* __ASM_ARM_REGS_S3C2416_MEM */ |