diff options
author | Haojian Zhuang <haojian.zhuang@marvell.com> | 2009-12-04 09:41:28 -0500 |
---|---|---|
committer | Eric Miao <eric.y.miao@gmail.com> | 2010-03-02 07:40:55 +0800 |
commit | 2f7e8faef5a50efaa1c173e99bdaa29e0129bb99 (patch) | |
tree | c73ae01004e110a87b7cf6cae686b9c142e2a63b /arch/arm/mach-mmp | |
parent | 978da5bcdb33f6e030fa3304662e2455a018f1b0 (diff) | |
download | linux-3.10-2f7e8faef5a50efaa1c173e99bdaa29e0129bb99.tar.gz linux-3.10-2f7e8faef5a50efaa1c173e99bdaa29e0129bb99.tar.bz2 linux-3.10-2f7e8faef5a50efaa1c173e99bdaa29e0129bb99.zip |
[ARM] mmp: add support for Marvell MMP2
Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's
ARMv6 compatible. Support basic interrupt handler and timer,
and basic support for MMP2 based FLINT platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r-- | arch/arm/mach-mmp/Kconfig | 18 | ||||
-rw-r--r-- | arch/arm/mach-mmp/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/common.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/flint.c | 123 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/cputype.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/devices.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/entry-macro.S | 7 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/irqs.h | 109 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mfp-mmp2.h | 236 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mmp2.h | 60 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 41 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-icu.h | 30 | ||||
-rw-r--r-- | arch/arm/mach-mmp/irq-mmp2.c | 138 | ||||
-rw-r--r-- | arch/arm/mach-mmp/mmp2.c | 83 | ||||
-rw-r--r-- | arch/arm/mach-mmp/time.c | 26 |
15 files changed, 890 insertions, 6 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index daddbefebf4..91631201e3f 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,6 @@ if ARCH_MMP -menu "Marvell PXA168/910 Implmentations" +menu "Marvell PXA168/910/MMP2 Implmentations" config MACH_ASPENITE bool "Marvell's PXA168 Aspenite Development Board" @@ -37,6 +37,16 @@ config MACH_TTC_DKB Say 'Y' here if you want to support the Marvell PXA910-based TTC_DKB Development Board. +config MACH_FLINT + bool "Marvell's Flint Development Platform" + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-based + Flint Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv6 architecture. + endmenu config CPU_PXA168 @@ -51,4 +61,10 @@ config CPU_PXA910 help Select code specific to PXA910 +config CPU_MMP2 + bool + select CPU_V6 + select CPU_32v6K + help + Select code specific to MMP2. MMP2 is ARMv6 compatible. endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index d4debb39023..698cd996cde 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -7,6 +7,7 @@ obj-y += common.o clock.o devices.o time.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o @@ -14,3 +15,4 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o +obj-$(CONFIG_MACH_FLINT) += flint.o diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index c33fbbc4941..85bf1245143 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -6,8 +6,10 @@ extern void timer_init(int irq); extern struct sys_timer pxa168_timer; extern struct sys_timer pxa910_timer; +extern struct sys_timer mmp2_timer; extern void __init pxa168_init_irq(void); extern void __init pxa910_init_irq(void); +extern void __init mmp2_init_irq(void); extern void __init icu_init_irq(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c new file mode 100644 index 00000000000..4ec7709a346 --- /dev/null +++ b/arch/arm/mach-mmp/flint.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-mmp/flint.c + * + * Support for the Marvell Flint Development Platform. + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/smc91x.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> + +#include "common.h" + +static unsigned long flint_pin_config[] __initdata = { + /* UART1 */ + GPIO45_UART1_RXD, + GPIO46_UART1_TXD, + + /* UART2 */ + GPIO47_UART2_RXD, + GPIO48_UART2_TXD, + + /* SMC */ + GPIO151_SMC_SCLK, + GPIO145_SMC_nCS0, + GPIO146_SMC_nCS1, + GPIO152_SMC_BE0, + GPIO153_SMC_BE1, + GPIO154_SMC_IRQ, + GPIO113_SMC_RDY, + + /*Ethernet*/ + GPIO155_GPIO155, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, +}; + +static struct smc91x_platdata flint_smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_resources[] = { + [0] = { + .start = SMC_CS1_PHYS_BASE + 0x300, + .end = SMC_CS1_PHYS_BASE + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gpio_to_irq(155), + .end = gpio_to_irq(155), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .dev = { + .platform_data = &flint_smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static void __init flint_init(void) +{ + mfp_config(ARRAY_AND_SIZE(flint_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(2); + + /* off-chip devices */ + platform_device_register(&smc91x_device); +} + +MACHINE_START(FLINT, "Flint Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = flint_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h index 25e797b0908..83b18721d93 100644 --- a/arch/arm/mach-mmp/include/mach/cputype.h +++ b/arch/arm/mach-mmp/include/mach/cputype.h @@ -8,6 +8,7 @@ * * PXA168 A0 0x41159263 0x56158400 0x00A0A333 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 + * MMP2 Z0 0x560f5811 */ #ifdef CONFIG_CPU_PXA168 @@ -24,7 +25,15 @@ # define __cpu_is_pxa910(id) (0) #endif +#ifdef CONFIG_CPU_MMP2 +# define __cpu_is_mmp2(id) \ + ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; }) +#else +# define __cpu_is_mmp2(id) (0) +#endif + #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) +#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); }) #endif /* __ASM_MACH_CPUTYPE_H */ diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index 24585397217..1fa0a492454 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -34,4 +34,16 @@ struct pxa_device_desc pxa910_device_##_name __initdata = { \ .size = _size, \ .dma = { _dma }, \ }; + +#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ +struct pxa_device_desc mmp2_device_##_name __initdata = { \ + .dev_name = "mmp2-" #_name, \ + .drv_name = _drv, \ + .id = _id, \ + .irq = IRQ_MMP2_##_irq, \ + .start = _start, \ + .size = _size, \ + .dma = { _dma }, \ +} + extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S index 6d3cd35478b..c42d9d4e892 100644 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -15,7 +15,12 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =ICU_AP_IRQ_SEL_INT_NUM + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + and \tmp, \tmp, #0xff00 + cmp \tmp, #0x5800 + ldr \base, =ICU_VIRT_BASE + addne \base, \base, #0x10c @ PJ1 AP INT SEL register + addeq \base, \base, #0x104 @ PJ4 IRQ SEL register .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d68871b0f28..f907cc9e08e 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -113,8 +113,113 @@ #define IRQ_PXA910_AP_PMU 60 #define IRQ_PXA910_SM_INT 63 /* from PinMux */ -#define IRQ_GPIO_START 64 -#define IRQ_GPIO_NUM 128 +/* + * Interrupt numbers for MMP2 + */ +#define IRQ_MMP2_NONE (-1) +#define IRQ_MMP2_SSP1 0 +#define IRQ_MMP2_SSP2 1 +#define IRQ_MMP2_SSPA1 2 +#define IRQ_MMP2_SSPA2 3 +#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ +#define IRQ_MMP2_RTC_MUX 5 +#define IRQ_MMP2_TWSI1 7 +#define IRQ_MMP2_GPU 8 +#define IRQ_MMP2_KEYPAD 9 +#define IRQ_MMP2_ROTARY 10 +#define IRQ_MMP2_TRACKBALL 11 +#define IRQ_MMP2_ONEWIRE 12 +#define IRQ_MMP2_TIMER1 13 +#define IRQ_MMP2_TIMER2 14 +#define IRQ_MMP2_TIMER3 15 +#define IRQ_MMP2_RIPC 16 +#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ +#define IRQ_MMP2_HDMI 19 +#define IRQ_MMP2_SSP3 20 +#define IRQ_MMP2_SSP4 21 +#define IRQ_MMP2_USB_HS1 22 +#define IRQ_MMP2_USB_HS2 23 +#define IRQ_MMP2_UART3 24 +#define IRQ_MMP2_UART1 27 +#define IRQ_MMP2_UART2 28 +#define IRQ_MMP2_MIPI_DSI 29 +#define IRQ_MMP2_CI2 30 +#define IRQ_MMP2_PMU_TIMER1 31 +#define IRQ_MMP2_PMU_TIMER2 32 +#define IRQ_MMP2_PMU_TIMER3 33 +#define IRQ_MMP2_USB_FS 34 +#define IRQ_MMP2_MISC_MUX 35 +#define IRQ_MMP2_WDT1 36 +#define IRQ_MMP2_NAND_DMA 37 +#define IRQ_MMP2_USIM 38 +#define IRQ_MMP2_MMC 39 +#define IRQ_MMP2_WTM 40 +#define IRQ_MMP2_LCD 41 +#define IRQ_MMP2_CI 42 +#define IRQ_MMP2_IRE 43 +#define IRQ_MMP2_USB_OTG 44 +#define IRQ_MMP2_NAND 45 +#define IRQ_MMP2_UART4 46 +#define IRQ_MMP2_DMA_FIQ 47 +#define IRQ_MMP2_DMA_RIQ 48 +#define IRQ_MMP2_GPIO 49 +#define IRQ_MMP2_SSP_MUX 51 +#define IRQ_MMP2_MMC2 52 +#define IRQ_MMP2_MMC3 53 +#define IRQ_MMP2_MMC4 54 +#define IRQ_MMP2_MIPI_HSI 55 +#define IRQ_MMP2_MSP 58 +#define IRQ_MMP2_MIPI_SLIM_DMA 59 +#define IRQ_MMP2_PJ4_FREQ_CHG 60 +#define IRQ_MMP2_MIPI_SLIM 62 +#define IRQ_MMP2_SM 63 + +#define IRQ_MMP2_MUX_BASE 64 + +/* secondary interrupt of INT #4 */ +#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) +#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) +#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) + +/* secondary interrupt of INT #5 */ +#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) +#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) +#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) + +/* secondary interrupt of INT #17 */ +#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) +#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) +#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) +#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) +#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) + +/* secondary interrupt of INT #35 */ +#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) +#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) +#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) +#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) +#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) +#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) +#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) +#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) +#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) +#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) +#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) +#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) +#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) +#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) +#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) + +/* secondary interrupt of INT #51 */ +#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) +#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) +#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) + +#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) + +#define IRQ_GPIO_START 128 +#define IRQ_GPIO_NUM 192 #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) #define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h new file mode 100644 index 00000000000..93715108534 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -0,0 +1,236 @@ +#ifndef __ASM_MACH_MFP_MMP2_H +#define __ASM_MACH_MFP_MMP2_H + +#include <mach/mfp.h> + +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + +/* GPIO */ + +/* DFI */ +#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) +#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0) +#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0) +#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0) +#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0) +#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0) +#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0) +#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0) +#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0) +#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0) +#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0) +#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0) +#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0) +#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0) +#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0) +#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0) +#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0) +#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0) +#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0) +#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0) +#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0) +#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0) +#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0) +#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0) + +/* Static Memory Controller */ +#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0) +#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0) +#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0) +#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0) +#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0) +#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0) +#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0) + +/* Ethernet */ +#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2) +#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) + +/* UART1 */ +#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1) +#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1) +#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1) +#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1) +#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1) +#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1) + +/* UART2 */ +#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1) +#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1) +#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1) +#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1) + +/* UART3 */ +#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1) +#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1) +#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1) +#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1) + +/* MMC1 */ +#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST) +#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST) +#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST) +#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST) +#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST) +#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST) +#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST) +#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST) +#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST) +#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST) +#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST) +#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST) + +/*MMC2*/ +#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST) +#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST) +#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST) +#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST) +#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST) +#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST) + +/*MMC3*/ +#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST) +#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST) +#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST) +#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST) +#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST) +#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST) +#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST) +#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST) +#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST) +#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST) + +/* LCD */ +#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST) +#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST) +#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST) +#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST) +#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST) +#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST) +#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST) +#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST) +#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST) +#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST) +#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST) +#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST) +#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST) +#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST) +#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST) +#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST) +#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST) +#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST) +#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST) +#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST) +#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST) +#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST) +#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST) +#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST) +#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST) +#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST) +#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST) +#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST) +#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST) +#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST) +#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST) +#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST) +#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST) + +#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST) + +/*LCD TV path*/ +#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST) +#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST) +#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST) +#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST) +#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST) +#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST) +#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST) +#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST) +#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST) +#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST) +#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST) +#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST) + +/* I2C */ +#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW) +#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW) +#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW) +#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW) +#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW) +#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW) +#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW) +#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW) + +/* SSPA1 */ +#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1) +#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1) +#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1) +#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1) + +/* SSPA2 */ +#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1) +#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1) +#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1) +#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1) + +/* Keypad */ +#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) +#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) +#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) +#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) +#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) +#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) +#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) +#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) +#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) +#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) +#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) +#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) +#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) +#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) +#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) +#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) +#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) +#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) +#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) +#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) +#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1) +#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1) +#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1) +#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1) + +/* CAMERA */ +#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST) +#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST) +#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST) +#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST) +#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST) +#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST) +#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST) +#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST) +#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST) +#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST) +#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST) +#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST) + +/* Wifi */ +#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) +#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) +#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) + +/* Codec*/ +#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) + + +#endif /* __ASM_MACH_MFP_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h new file mode 100644 index 00000000000..459f3be9cfb --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -0,0 +1,60 @@ +#ifndef __ASM_MACH_MMP2_H +#define __ASM_MACH_MMP2_H + +#include <linux/i2c.h> +#include <mach/devices.h> +#include <plat/i2c.h> + +extern struct pxa_device_desc mmp2_device_uart1; +extern struct pxa_device_desc mmp2_device_uart2; +extern struct pxa_device_desc mmp2_device_uart3; +extern struct pxa_device_desc mmp2_device_uart4; +extern struct pxa_device_desc mmp2_device_twsi1; +extern struct pxa_device_desc mmp2_device_twsi2; +extern struct pxa_device_desc mmp2_device_twsi3; +extern struct pxa_device_desc mmp2_device_twsi4; +extern struct pxa_device_desc mmp2_device_twsi5; +extern struct pxa_device_desc mmp2_device_twsi6; + +static inline int mmp2_add_uart(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &mmp2_device_uart1; break; + case 2: d = &mmp2_device_uart2; break; + case 3: d = &mmp2_device_uart3; break; + case 4: d = &mmp2_device_uart4; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, NULL, 0); +} + +static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, + struct i2c_board_info *info, unsigned size) +{ + struct pxa_device_desc *d = NULL; + int ret; + + switch (id) { + case 0: d = &mmp2_device_twsi1; break; + case 1: d = &mmp2_device_twsi2; break; + case 2: d = &mmp2_device_twsi3; break; + case 3: d = &mmp2_device_twsi4; break; + case 4: d = &mmp2_device_twsi5; break; + case 5: d = &mmp2_device_twsi6; break; + default: + return -EINVAL; + } + + ret = i2c_register_board_info(id, info, size); + if (ret) + return ret; + + return pxa_register_device(d, data, sizeof(*data)); +} + +#endif /* __ASM_MACH_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 98ccbee4bd0..712af03fd1a 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -69,6 +69,47 @@ #define APBC_PXA910_ASFAR APBC_REG(0x050) #define APBC_PXA910_ASSAR APBC_REG(0x054) +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_MMP2_RTC APBC_REG(0x000) +#define APBC_MMP2_TWSI1 APBC_REG(0x004) +#define APBC_MMP2_TWSI2 APBC_REG(0x008) +#define APBC_MMP2_TWSI3 APBC_REG(0x00c) +#define APBC_MMP2_TWSI4 APBC_REG(0x010) +#define APBC_MMP2_ONEWIRE APBC_REG(0x014) +#define APBC_MMP2_KPC APBC_REG(0x018) +#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) +#define APBC_MMP2_SW_JTAG APBC_REG(0x020) +#define APBC_MMP2_TIMERS APBC_REG(0x024) +#define APBC_MMP2_UART1 APBC_REG(0x02c) +#define APBC_MMP2_UART2 APBC_REG(0x030) +#define APBC_MMP2_UART3 APBC_REG(0x034) +#define APBC_MMP2_GPIO APBC_REG(0x038) +#define APBC_MMP2_PWM0 APBC_REG(0x03c) +#define APBC_MMP2_PWM1 APBC_REG(0x040) +#define APBC_MMP2_PWM2 APBC_REG(0x044) +#define APBC_MMP2_PWM3 APBC_REG(0x048) +#define APBC_MMP2_SSP0 APBC_REG(0x04c) +#define APBC_MMP2_SSP1 APBC_REG(0x050) +#define APBC_MMP2_SSP2 APBC_REG(0x054) +#define APBC_MMP2_SSP3 APBC_REG(0x058) +#define APBC_MMP2_SSP4 APBC_REG(0x05c) +#define APBC_MMP2_SSP5 APBC_REG(0x060) +#define APBC_MMP2_AIB APBC_REG(0x064) +#define APBC_MMP2_ASFAR APBC_REG(0x068) +#define APBC_MMP2_ASSAR APBC_REG(0x06c) +#define APBC_MMP2_USIM APBC_REG(0x070) +#define APBC_MMP2_MPMU APBC_REG(0x074) +#define APBC_MMP2_IPC APBC_REG(0x078) +#define APBC_MMP2_TWSI5 APBC_REG(0x07c) +#define APBC_MMP2_TWSI6 APBC_REG(0x080) +#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) +#define APBC_MMP2_UART4 APBC_REG(0x088) +#define APBC_MMP2_RIPC APBC_REG(0x08c) +#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ +#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) + /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h index e5f08723e0c..02b8bf83acb 100644 --- a/arch/arm/mach-mmp/include/mach/regs-icu.h +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h @@ -17,10 +17,12 @@ #define ICU_REG(x) (ICU_VIRT_BASE + (x)) #define ICU_INT_CONF(n) ICU_REG((n) << 2) +#define ICU_INT_CONF_MASK (0xf) + +/************ PXA168/PXA910 (MMP) *********************/ #define ICU_INT_CONF_AP_INT (1 << 6) #define ICU_INT_CONF_CP_INT (1 << 5) #define ICU_INT_CONF_IRQ (1 << 4) -#define ICU_INT_CONF_MASK (0xf) #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ @@ -28,4 +30,30 @@ #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ +/************************** MMP2 ***********************/ + +/* + * IRQ0/FIQ0 is routed to SP IRQ/FIQ. + * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. + */ +#define ICU_INT_ROUTE_SP_IRQ (1 << 4) +#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) +#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) + +#define MMP2_ICU_INT4_STATUS ICU_REG(0x150) +#define MMP2_ICU_INT5_STATUS ICU_REG(0x154) +#define MMP2_ICU_INT17_STATUS ICU_REG(0x158) +#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) +#define MMP2_ICU_INT51_STATUS ICU_REG(0x160) + +#define MMP2_ICU_INT4_MASK ICU_REG(0x168) +#define MMP2_ICU_INT5_MASK ICU_REG(0x16C) +#define MMP2_ICU_INT17_MASK ICU_REG(0x170) +#define MMP2_ICU_INT35_MASK ICU_REG(0x174) +#define MMP2_ICU_INT51_MASK ICU_REG(0x178) + +#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) +#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) +#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) + #endif /* __ASM_MACH_ICU_H */ diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c new file mode 100644 index 00000000000..dcd36f4bc9d --- /dev/null +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -0,0 +1,138 @@ +/* + * linux/arch/arm/mach-mmp/irq-mmp2.c + * + * Generic IRQ handling, GPIO IRQ demultiplexing, etc. + * + * Author: Haojian Zhuang <haojian.zhuang@marvell.com> + * Copyright: Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/regs-icu.h> + +#include "common.h" + +static void icu_mask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r &= ~ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static void icu_unmask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r |= ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static struct irq_chip icu_irq_chip = { + .name = "icu_irq", + .mask_ack = icu_mask_irq, + .unmask = icu_unmask_irq, +}; + +#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +static void _name_##_mask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +static void _name_##_unmask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \ +{ \ + unsigned long status, mask, n; \ + mask = __raw_readl(prefix##_MASK); \ + while (1) { \ + status = __raw_readl(prefix##_STATUS) & ~mask; \ + if (status == 0) \ + break; \ + n = find_first_bit(&status, BITS_PER_LONG); \ + while (n < BITS_PER_LONG) { \ + generic_handle_irq(irq_base + n); \ + n = find_next_bit(&status, BITS_PER_LONG, n+1); \ + } \ + } \ +} + +#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \ +SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static struct irq_chip _name_##_irq_chip = { \ + .name = #_name_, \ + .mask_ack = _name_##_mask_irq, \ + .unmask = _name_##_unmask_irq, \ +} + +SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); +SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5); +SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17); +SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35); +SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); + +static void init_mux_irq(struct irq_chip *chip, int start, int num) +{ + int irq; + + for (irq = start; num > 0; irq++, num--) { + chip->mask_ack(irq); + set_irq_chip(irq, chip); + set_irq_flags(irq, IRQF_VALID); + set_irq_handler(irq, handle_level_irq); + } +} + +void __init mmp2_init_irq(void) +{ + int irq; + + for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { + icu_mask_irq(irq); + set_irq_chip(irq, &icu_irq_chip); + set_irq_flags(irq, IRQF_VALID); + + switch (irq) { + case IRQ_MMP2_PMIC_MUX: + case IRQ_MMP2_RTC_MUX: + case IRQ_MMP2_TWSI_MUX: + case IRQ_MMP2_MISC_MUX: + case IRQ_MMP2_SSP_MUX: + break; + default: + set_irq_handler(irq, handle_level_irq); + break; + } + } + + init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); + init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); + init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); + init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); + init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); + + set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); +} diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c new file mode 100644 index 00000000000..a9ca93d9741 --- /dev/null +++ b/arch/arm/mach-mmp/mmp2.c @@ -0,0 +1,83 @@ +/* + * linux/arch/arm/mach-mmp/mmp2.c + * + * code name MMP2 + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <mach/addr-map.h> +#include <mach/regs-apbc.h> +#include <mach/regs-apmu.h> +#include <mach/cputype.h> +#include <mach/irqs.h> +#include <mach/mfp.h> +#include <mach/devices.h> + +#include "common.h" +#include "clock.h" + +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +/* APB peripheral clocks */ +static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); +static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); +static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); +static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); +static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); +static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); +static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); +static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); +static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); +static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(rtc, MMP2_RTC, 0, 32768); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), +}; + +static int __init mmp2_init(void) +{ + if (cpu_is_mmp2()) { + mfp_init_base(MFPR_VIRT_BASE); + clks_register(ARRAY_AND_SIZE(mmp2_clkregs)); + } + + return 0; +} +postcore_initcall(mmp2_init); + +/* on-chip devices */ +MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); +MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); +MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); +MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); +MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); +MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); +MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); +MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); +MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); +MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); +MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); + diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index a8400bb891e..cf75694e968 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -30,7 +30,10 @@ #include <mach/addr-map.h> #include <mach/regs-timers.h> +#include <mach/regs-apbc.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include <asm/mach/time.h> #include "clock.h" @@ -158,7 +161,7 @@ static void __init timer_config(void) __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ - ccr &= TMR_CCR_CS_0(0x3); + ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); /* free-running mode */ @@ -197,3 +200,24 @@ void __init timer_init(int irq) clocksource_register(&cksrc); clockevents_register_device(&ckevt); } + +static void __init mmp2_timer_init(void) +{ + unsigned long clk_rst; + + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + + /* + * enable bus/functional clock, enable 6.5MHz (divider 4), + * release reset + */ + clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); + + timer_init(IRQ_MMP2_TIMER1); +} + +struct sys_timer mmp2_timer = { + .init = mmp2_timer_init, +}; + |