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author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-22 10:18:41 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-22 15:32:39 +0100 |
commit | 2b254693bef4f1299de0afb231890fe348df11c6 (patch) | |
tree | 33faef980ce73948ec96f32c9f4ae9c4ba5d9a12 /arch/arm/mach-imx/clk-pllv3.c | |
parent | 7a04092c733fd72ded1294719046cfdb31feced3 (diff) | |
download | linux-3.10-2b254693bef4f1299de0afb231890fe348df11c6.tar.gz linux-3.10-2b254693bef4f1299de0afb231890fe348df11c6.tar.bz2 linux-3.10-2b254693bef4f1299de0afb231890fe348df11c6.zip |
ARM i.MX6: remove gate_mask from pllv3
Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/clk-pllv3.c')
-rw-r--r-- | arch/arm/mach-imx/clk-pllv3.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 59e74339ab0..d09bc3df9a7 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -31,7 +31,6 @@ * @clk_hw: clock source * @base: base address of PLL registers * @powerup_set: set POWER bit to power up the PLL - * @gate_mask: mask of gate bits * @div_mask: mask of divider bits * * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 @@ -41,7 +40,6 @@ struct clk_pllv3 { struct clk_hw hw; void __iomem *base; bool powerup_set; - u32 gate_mask; u32 div_mask; }; @@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw) u32 val; val = readl_relaxed(pll->base); - val |= pll->gate_mask; + val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); return 0; @@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw) u32 val; val = readl_relaxed(pll->base); - val &= ~pll->gate_mask; + val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); } @@ -307,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = { struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, - u32 gate_mask, u32 div_mask) + u32 div_mask) { struct clk_pllv3 *pll; const struct clk_ops *ops; @@ -339,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ops = &clk_pllv3_ops; } pll->base = base; - pll->gate_mask = gate_mask; pll->div_mask = div_mask; init.name = name; |