devfreq: exynos: Add Exynos3250 busfreq support

This patch add Exynos3250 busfreq driver to support DVFS(Dynamic Voltage
Frequency Scaling) about Exynos3250's Memory interface and bus. Exynos3250
busfreq driver will optimize power-consumption/performance of memory according
to PPMU(Profiling Performance Monitoring Unit) Read/Write count of Exynos3250
SoC.

- Exynos3250 MIF (DMC block) use following PPMU to check utilization
of MIF block.
: PPMU_DMC0
: PPMU_DMC1

- Exynos3250 INT (Internal block except for ARM/DMC/G3D) use following PPMU
to check utilization of INT block.
: PPMU_LEFT
: PPMU_RIGHT

Change-Id: If35c1fa0228f16547015931c64b0d6e896599d46
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

1 files changed, 126 insertions, 1 deletions

diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 5e0f6c41006..138d77f3557 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -18,9 +18,134 @@
 
 #define EXYNOS_CLKREG(x)			(S5P_VA_CMU + (x))
 
+/* EXYNOS3250 */
 #define EXYNOS3_MIF_R_REG(x)			(S5P_VA_CMU_ACP + (x))		/* 0x1045_0000 */
-#define EXYNOS3_CLKSRC_ACP			EXYNOS3_MIF_R_REG(0x0300)
+#define EXYNOS3_MIF_L_REG(x)			(S5P_VA_CMU_DMC + (x))		/* 0x105c_0000 */
+
+#define EXYNOS3_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0xC310)
+#define EXYNOS3_CLKSRC_MASK_CAM			EXYNOS_CLKREG(0xC320)
+
+#define EXYNOS3_CLKSRC_MASK_LCD			EXYNOS_CLKREG(0xC334)
+#define EXYNOS3_CLKSRC_MASK_ISP			EXYNOS_CLKREG(0xC338)
+#define EXYNOS3_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0xC340)
+#define EXYNOS3_CLKSRC_MASK_PERIL0		EXYNOS_CLKREG(0xC350)
+#define EXYNOS3_CLKSRC_MASK_PERIL1		EXYNOS_CLKREG(0xC354)
 
+#define EXYNOS3_CLKGATE_IP_MFC			EXYNOS_CLKREG(0xC928)
+#define EXYNOS3_CLKGATE_IP_LCD			EXYNOS_CLKREG(0xC934)
+#define EXYNOS3_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0xC940)
+#define EXYNOS3_CLKGATE_IP_PERIL		EXYNOS_CLKREG(0xC950)
+
+#define EXYNOS3_CLKDIV_LEFTBUS			EXYNOS_CLKREG(0x4500)
+#define EXYNOS3_CLKDIV_RIGHTBUS			EXYNOS_CLKREG(0x8500)
+#define EXYNOS3_CLKDIV_TOP			EXYNOS_CLKREG(0xC510)
+#define EXYNOS3_CLKDIV_MFC			EXYNOS_CLKREG(0xC528)
+
+#define EXYNOS3_CLKSRC_ACP			EXYNOS3_MIF_R_REG(0x0300)
+#define EXYNOS3_CLKSRC_MASK_ACP			EXYNOS3_MIF_R_REG(0x0304)
+#define EXYNOS3_CLKDIV_ACP0			EXYNOS3_MIF_R_REG(0x0500)
+
+#define EXYNOS3_CLKDIV_DMC1			EXYNOS3_MIF_L_REG(0x0504)
+
+#define EXYNOS3_CLKDIV_DMC1_DMC_SHIFT		(27)
+#define EXYNOS3_CLKDIV_DMC1_DMC_MASK		(0x7 << EXYNOS3_CLKDIV_DMC1_DMC_SHIFT)
+#define EXYNOS3_CLKDIV_DMC1_DPHY_SHIFT		(23)
+#define EXYNOS3_CLKDIV_DMC1_DPHY_MASK		(0x7 << EXYNOS3_CLKDIV_DMC1_DPHY_SHIFT)
+#define EXYNOS3_CLKDIV_DMC1_DMC_PRE_SHIFT	(19)
+#define EXYNOS3_CLKDIV_DMC1_DMC_PRE_MASK	(0x3 << EXYNOS3_CLKDIV_DMC1_DMC_PRE_SHIFT)
+#define EXYNOS3_CLKDIV_DMC1_DMCP_SHIFT		(15)
+#define EXYNOS3_CLKDIV_DMC1_DMCP_MASK		(0x7 << EXYNOS3_CLKDIV_DMC1_DMCP_SHIFT)
+#define EXYNOS3_CLKDIV_DMC1_DMCD_SHIFT		(11)
+#define EXYNOS3_CLKDIV_DMC1_DMCD_MASK		(0x7 << EXYNOS3_CLKDIV_DMC1_DMCD_SHIFT)
+
+#define EXYNOS3_CLKDIV_LEFTBUS_GPL_SHIFT	(4)
+#define EXYNOS3_CLKDIV_LEFTBUS_GPL_MASK		(0x7 << EXYNOS3_CLKDIV_LEFTBUS_GPL_SHIFT)
+#define EXYNOS3_CLKDIV_LEFTBUS_GDL_SHIFT	(0)
+#define EXYNOS3_CLKDIV_LEFTBUS_GDL_MASK		(0xF << EXYNOS3_CLKDIV_LEFTBUS_GDL_SHIFT)
+
+#define EXYNOS3_CLKDIV_RIGHTBUS_GPR_SHIFT	(4)
+#define EXYNOS3_CLKDIV_RIGHTBUS_GPR_MASK	(0x7 << EXYNOS3_CLKDIV_RIGHTBUS_GPR_SHIFT)
+#define EXYNOS3_CLKDIV_RIGHTBUS_GDR_SHIFT	(0)
+#define EXYNOS3_CLKDIV_RIGHTBUS_GDR_MASK	(0xF << EXYNOS3_CLKDIV_RIGHTBUS_GDR_SHIFT)
+
+#define EXYNOS3_CLKDIV_TOP_ACLK_400_SHIFT	(24)
+#define EXYNOS3_CLKDIV_TOP_ACLK_400_MASK	(0x7 << EXYNOS3_CLKDIV_TOP_ACLK_400_SHIFT)
+#define EXYNOS3_CLKDIV_TOP_ACLK_200_SHIFT	(12)
+#define EXYNOS3_CLKDIV_TOP_ACLK_200_MASK	(0x7 << EXYNOS3_CLKDIV_TOP_ACLK_200_SHIFT)
+#define EXYNOS3_CLKDIV_TOP_ACLK_160_SHIFT	(8)
+#define EXYNOS3_CLKDIV_TOP_ACLK_160_MASK	(0x7 << EXYNOS3_CLKDIV_TOP_ACLK_160_SHIFT)
+#define EXYNOS3_CLKDIV_TOP_ACLK_100_SHIFT	(4)
+#define EXYNOS3_CLKDIV_TOP_ACLK_100_MASK	(0xF << EXYNOS3_CLKDIV_TOP_ACLK_100_SHIFT)
+#define EXYNOS3_CLKDIV_TOP_ACLK_266_SHIFT	(0)
+#define EXYNOS3_CLKDIV_TOP_ACLK_266_MASK	(0x7 << EXYNOS3_CLKDIV_TOP_ACLK_266_SHIFT)
+
+#define EXYNOS3_CLKDIV_ACP0_SHIFT		(0)
+#define EXYNOS3_CLKDIV_ACP0_MASK		(0x7 << EXYNOS3_CLKDIV_ACP0_SHIFT)
+#define EXYNOS3_CLKDIV_ACP0_PCLK_SHIFT		(4)
+#define EXYNOS3_CLKDIV_ACP0_PCLK_MASK		(0x7 << EXYNOS3_CLKDIV_ACP0_PCLK_SHIFT)
+#define EXYNOS3_CLKDIV_ACP0_DMC_SHIFT		(8)
+#define EXYNOS3_CLKDIV_ACP0_DMC_MASK		(0x7 << EXYNOS3_CLKDIV_ACP0_DMC_SHIFT)
+#define EXYNOS3_CLKDIV_ACP0_CORED_SHIFT		(12)
+#define EXYNOS3_CLKDIV_ACP0_CORED_MASK		(0x7 << EXYNOS3_CLKDIV_ACP0_CORED_SHIFT)
+#define EXYNOS3_CLKDIV_ACP0_COREP_SHIFT		(16)
+#define EXYNOS3_CLKDIV_ACP0_COREP_MASK		(0x7 << EXYNOS3_CLKDIV_ACP0_COREP_SHIFT)
+
+#define EXYNOS3_CLKDIV_MFC_SHIFT		(0)
+#define EXYNOS3_CLKDIV_MFC_MASK			(0x7 << EXYNOS3_CLKDIV_MFC_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_LEFTBUS		EXYNOS_CLKREG(0x4600)
+#define EXYNOS3_CLKDIV_STAT_RIGHTBUS		EXYNOS_CLKREG(0x8600)
+#define EXYNOS3_CLKDIV_STAT_TOP			EXYNOS_CLKREG(0xC610)
+#define EXYNOS3_CLKDIV_STAT_MFC			EXYNOS_CLKREG(0xC628)
+#define EXYNOS3_CLKDIV_STAT_ACP0		EXYNOS3_MIF_R_REG(0x0600)
+#define EXYNOS3_CLKDIV_STAT_DMC0		EXYNOS3_MIF_L_REG(0x0600)
+#define EXYNOS3_CLKDIV_STAT_DMC1		EXYNOS3_MIF_L_REG(0x0604)
+
+#define EXYNOS3_CLKDIV_STAT_LEFTBUS_GPL_SHIFT	(4)
+#define EXYNOS3_CLKDIV_STAT_LEFTBUS_GPL_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_LEFTBUS_GPL_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_LEFTBUS_GDL_SHIFT	(0)
+#define EXYNOS3_CLKDIV_STAT_LEFTBUS_GDL_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_LEFTBUS_GDL_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_RIGHTBUS_GPR_SHIFT	(4)
+#define EXYNOS3_CLKDIV_STAT_RIGHTBUS_GPR_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_RIGHTBUS_GPR_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_RIGHTBUS_GDR_SHIFT	(0)
+#define EXYNOS3_CLKDIV_STAT_RIGHTBUS_GDR_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_RIGHTBUS_GDR_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_400_SHIFT	(24)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_400_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_TOP_ACLK_400_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_200_SHIFT	(12)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_200_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_TOP_ACLK_200_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_160_SHIFT	(8)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_160_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_TOP_ACLK_160_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_100_SHIFT	(4)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_100_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_TOP_ACLK_100_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_266_SHIFT	(0)
+#define EXYNOS3_CLKDIV_STAT_TOP_ACLK_266_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_TOP_ACLK_266_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMC_PRE_SHIFT	(16)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMC_PRE_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_DMC0_DMC_PRE_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMCP_SHIFT	(12)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMCP_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_DMC0_DMCP_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMCD_SHIFT	(8)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMCD_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_DMC0_DMCD_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMC_SHIFT	(4)
+#define EXYNOS3_CLKDIV_STAT_DMC0_DMC_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_DMC0_DMC_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_ACP0_COREP_SHIFT	(16)
+#define EXYNOS3_CLKDIV_STAT_ACP0_COREP_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_ACP0_COREP_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_ACP0_CORED_SHIFT	(12)
+#define EXYNOS3_CLKDIV_STAT_ACP0_CORED_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_ACP0_CORED_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_ACP0_DMC_SHIFT	(8)
+#define EXYNOS3_CLKDIV_STAT_ACP0_DMC_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_ACP0_DMC_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_ACP0_PCLK_SHIFT	(4)
+#define EXYNOS3_CLKDIV_STAT_ACP0_PCLK_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_ACP0_PCLK_SHIFT)
+#define EXYNOS3_CLKDIV_STAT_ACP0_ACP_SHIFT	(0)
+#define EXYNOS3_CLKDIV_STAT_ACP0_ACP_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_ACP0_ACP_SHIFT)
+
+#define EXYNOS3_CLKDIV_STAT_MFC_MFC_SHIFT	(0)
+#define EXYNOS3_CLKDIV_STAT_MFC_MFC_MASK	(0x1 << EXYNOS3_CLKDIV_STAT_MFC_MFC_SHIFT)
+
+/* EXYNOS4 */
 #define EXYNOS4_CLKDIV_LEFTBUS			EXYNOS_CLKREG(0x04500)
 #define EXYNOS4_CLKDIV_STAT_LEFTBUS		EXYNOS_CLKREG(0x04600)
 #define EXYNOS4_CLKGATE_IP_LEFTBUS		EXYNOS_CLKREG(0x04800)