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authorChanwoo Choi <cw00.choi@samsung.com>2014-07-10 21:37:13 +0900
committerChanho Park <chanho61.park@samsung.com>2014-11-18 12:00:12 +0900
commit9a81acaa551c9dbc47e5129381d924882f158b30 (patch)
treee050e5697f5a54528128b2dbea61af6c0b087691 /arch/arm/mach-exynos/include/mach
parent43b8bfbf2fcfcf54431518392d0115a3c98352f6 (diff)
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ARM: EXYNOS: Add support for suspend-to-ram of Exynos3250
This patch add support for suspend-to-ram of Exynos3250 based on Cortex-A7 dual-core. The Exynos3250 hasn't L2 cache. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach')
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h3
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h6
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 0cf9ad0af65..5e0f6c41006 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -18,6 +18,9 @@
#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
+#define EXYNOS3_MIF_R_REG(x) (S5P_VA_CMU_ACP + (x)) /* 0x1045_0000 */
+#define EXYNOS3_CLKSRC_ACP EXYNOS3_MIF_R_REG(0x0300)
+
#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 3fa864e9de1..05d405ab655 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -163,12 +163,14 @@
#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
+#define S5P_PAD_RET_MMC2_OPTION S5P_PMUREG(0x30C8)
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
+#define S5P_PAD_RET_SPI_OPTION S5P_PMUREG(0x31C8)
#define S5P_PS_HOLD_CONTROL S5P_PMUREG(0x330C)
#define S5P_PS_HOLD_EN (1 << 31)
@@ -266,6 +268,8 @@
/* For EXYNOS3 */
#define EXYNOS3_COREPORESET(cpu) ((1 << 4) << cpu)
+#define EXYNOS3_CENTRAL_SEQ_CONFIGURATION_COREBLK S5P_PMUREG(0x0240)
+
#define EXYNOS3_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
@@ -361,6 +365,7 @@
#define EXYNOS3_ARM_CORE_OPTION(_nr) (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
#define EXYNOS3_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
+#define EXYNOS3_ARM_L2_OPTION S5P_PMUREG(0x2608)
#define EXYNOS3_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define EXYNOS3_CORE_TOP_PWR_OPTION S5P_PMUREG(0x2CA8)
#define EXYNOS3_CORE_TOP_PWR_DURATION S5P_PMUREG(0x2CB0)
@@ -373,6 +378,7 @@
#define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0)
#define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
+#define EXYNOS3_OPTION_USE_RETENTION (1 << 4)
/* For EXYNOS5 */