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| author | Marc Zyngier <marc.zyngier@arm.com> | 2013-06-21 13:08:47 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-08-20 08:43:03 -0700 |
| commit | 285695e4211008e0f06648c3ae7af8ba09a88399 (patch) | |
| tree | 44458c6c3ff6270219236ef7c7f7bbbd7cd1a219 /arch/arm/kvm | |
| parent | 921fa4d670d801e9394f843dd14e2d7faabbba4a (diff) | |
| download | linux-3.10-285695e4211008e0f06648c3ae7af8ba09a88399.tar.gz linux-3.10-285695e4211008e0f06648c3ae7af8ba09a88399.tar.bz2 linux-3.10-285695e4211008e0f06648c3ae7af8ba09a88399.zip | |
ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
commit 479c5ae2f8a55509b691494cd13691d3dc31d102 upstream.
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.
For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/kvm')
| -rw-r--r-- | arch/arm/kvm/interrupts.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index d0a8fa33409..20e03d96955 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -49,6 +49,7 @@ __kvm_hyp_code_start: ENTRY(__kvm_tlb_flush_vmid_ipa) push {r2, r3} + dsb ishst add r0, r0, #KVM_VTTBR ldrd r2, r3, [r0] mcrr p15, 6, r2, r3, c2 @ Write VTTBR |