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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-14 10:59:32 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-14 10:59:32 +0100
commit98797a241e28b787b84d308b867ec4c5fe7bbdf8 (patch)
treeedd39824d91bd8cf33d8903e10ed337611483360 /arch/arm/Kconfig
parentca8cbc8391cbd4d6e4304fc6b62682ed93d2b165 (diff)
parentc626e3f5ca1d95ad2204d3128c26e7678714eb55 (diff)
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Merge branch 'copy_user' of git://git.marvell.com/orion into devel
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c857111ab96..3473f8b8ede 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1091,6 +1091,22 @@ config ALIGNMENT_TRAP
correct operation of some network protocols. With an IP-only
configuration it is safe to say N, otherwise say Y.
+config UACCESS_WITH_MEMCPY
+ bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
+ depends on MMU && EXPERIMENTAL
+ default y if CPU_FEROCEON
+ help
+ Implement faster copy_to_user and clear_user methods for CPU
+ cores where a 8-word STM instruction give significantly higher
+ memory write throughput than a sequence of individual 32bit stores.
+
+ A possible side effect is a slight increase in scheduling latency
+ between threads sharing the same address space if they invoke
+ such copy operations with large buffers.
+
+ However, if the CPU data cache is using a write-allocate mode,
+ this option is unlikely to provide any performance gain.
+
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