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| author | Cheng Renquan <crq@kernel.org> | 2009-05-26 16:03:07 +0800 |
|---|---|---|
| committer | Sam Ravnborg <sam@ravnborg.org> | 2009-06-09 22:37:45 +0200 |
| commit | b8b0618cf6fab3bd5b1da8c72f4b29847d81ac42 (patch) | |
| tree | ca98af18492ddc48eb298dfb94a603d30ba3e444 /Makefile | |
| parent | 3e56f08bffe9e3e2b936eb73bd51d8800d1b42c2 (diff) | |
| download | linux-3.10-b8b0618cf6fab3bd5b1da8c72f4b29847d81ac42.tar.gz linux-3.10-b8b0618cf6fab3bd5b1da8c72f4b29847d81ac42.tar.bz2 linux-3.10-b8b0618cf6fab3bd5b1da8c72f4b29847d81ac42.zip | |
kbuild: remove extra ifdef/endif of top Makefile
The GNU make's origin function know undefined variable well,
so the outer ifdef/endif conditional checking is unneeded.
From `info make` documentation, origin will return
`undefined'
if VARIABLE was never defined.
`command line'
if VARIABLE was defined on the command line.
...
Therefore, $(origin V) will get a value anyway, killing ifdef/endif is
viable and safe.
Furthermore, I've checked the minimal requirements from
Documentation/Changes is GNU make 3.79.1, and that version of GNU make
has support of origin function well already, so now it's safe to kill
the outer conditional checking, without upgrading the minimal
requirements.
Signed-off-by: Cheng Renquan <crq@kernel.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 26 |
1 files changed, 9 insertions, 17 deletions
@@ -35,10 +35,8 @@ MAKEFLAGS += -rR --no-print-directory # To put more focus on warnings, be less verbose as default # Use 'make V=1' to see the full commands -ifdef V - ifeq ("$(origin V)", "command line") - KBUILD_VERBOSE = $(V) - endif +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) endif ifndef KBUILD_VERBOSE KBUILD_VERBOSE = 0 @@ -54,10 +52,8 @@ endif # See the file "Documentation/sparse.txt" for more details, including # where to get the "sparse" utility. -ifdef C - ifeq ("$(origin C)", "command line") - KBUILD_CHECKSRC = $(C) - endif +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) endif ifndef KBUILD_CHECKSRC KBUILD_CHECKSRC = 0 @@ -69,12 +65,10 @@ endif ifdef SUBDIRS KBUILD_EXTMOD ?= $(SUBDIRS) endif -ifdef M - ifeq ("$(origin M)", "command line") - KBUILD_EXTMOD := $(M) - endif -endif +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif # kbuild supports saving output files in a separate directory. # To locate output files in a separate directory two syntaxes are supported. @@ -98,10 +92,8 @@ ifeq ($(KBUILD_SRC),) # OK, Make called in directory where kernel src resides # Do we want to locate output files in a separate directory? -ifdef O - ifeq ("$(origin O)", "command line") - KBUILD_OUTPUT := $(O) - endif +ifeq ("$(origin O)", "command line") + KBUILD_OUTPUT := $(O) endif # That's our default target when none is given on the command line |