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authorLuck, Tony <>2008-01-14 09:59:24 -0800
committerTony Luck <>2008-01-15 14:26:55 -0800
commit1a499150e4ec1299232e24389f648d059ce5617a (patch)
treeed83bc200faa49a67a18f6ca331f7e9275e43b13 /Makefile
parent0938e7586440ac97cedc0f5528a8684ebfa4ce43 (diff)
[IA64] Fix unaligned handler for floating point instructions with base update
The compiler team did the hard work for this distilling a problem in large fortran application which showed up when applied to a 290MB input data set down to this instruction: ldfd f34=[r17],-8 Which they noticed incremented r17 by 0x10 rather than decrementing it by 8 when the value in r17 caused an unaligned data fault. I tracked it down to some bad instruction decoding in unaligned.c. The code assumes that the 'x' bit can determine whether the instruction is an "ldf" or "ldfp" ... which it is for opcode=6 (see table 4-29 on page 3:302 of the SDM). But for opcode=7 the 'x' bit is irrelevent, all variants are "ldf" instructions (see table 4-36 on page 3:306). Note also that interpreting the instruction as "ldfp" means that the "paired" floating point register (f35 in the example here) will also be corrupted. Signed-off-by: Tony Luck <>
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