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author | Arnd Bergmann <arnd@arndb.de> | 2011-11-02 02:46:10 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2011-11-02 02:46:10 +0100 |
commit | 884897e6a10a86de0e611a76f4bf3fd0068a672c (patch) | |
tree | 019689fb9d129404af1efba4df10975bc9e0a57a /Documentation | |
parent | c72dbae971400e466ad9ff16c920cd6d9d8c55a1 (diff) | |
parent | 8b61f37440388ebbd2a894178fe098f2e70ab392 (diff) | |
download | linux-3.10-884897e6a10a86de0e611a76f4bf3fd0068a672c.tar.gz linux-3.10-884897e6a10a86de0e611a76f4bf3fd0068a672c.tar.bz2 linux-3.10-884897e6a10a86de0e611a76f4bf3fd0068a672c.zip |
Merge branch 'highbank/soc' into next/soc
Conflicts:
arch/arm/mach-mxs/include/mach/gpio.h
arch/arm/mach-omap2/board-generic.c
arch/arm/plat-mxc/include/mach/gpio.h
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda.txt | 8 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/arm/l2cc.txt | 44 |
2 files changed, 52 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt new file mode 100644 index 00000000000..4755caaccba --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.txt @@ -0,0 +1,8 @@ +Calxeda Highbank Platforms Device Tree Bindings +----------------------------------------------- + +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following +properties. + +Required root node properties: + - compatible = "calxeda,highbank"; diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt new file mode 100644 index 00000000000..7ca52161e7a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -0,0 +1,44 @@ +* ARM L2 Cache Controller + +ARM cores often have a separate level 2 cache controller. There are various +implementations of the L2 cache controller with compatible programming models. +The ARM L2 cache representation in the device tree should be done as follows: + +Required properties: + +- compatible : should be one of: + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" +- cache-unified : Specifies the cache is a unified cache. +- cache-level : Should be set to 2 for a level 2 cache. +- reg : Physical base address and size of cache controller's memory mapped + registers. + +Optional properties: + +- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. +- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. +- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. +- arm,filter-ranges : <start length> Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. +- interrupts : 1 combined interrupt. + +Example: + +L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-latency = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; +}; |