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| author | Andre Przywara <andre.przywara@amd.com> | 2011-04-16 02:27:53 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-04-19 10:07:54 +0200 |
| commit | 83112e688f5f05dea1e63787db9a6c16b2887a1d (patch) | |
| tree | a8f89610d85895e5f3eeb81c4ee340747a06987b | |
| parent | 5d2cd90922c778908bd0cd669e572a5b5eafd737 (diff) | |
| download | linux-3.10-83112e688f5f05dea1e63787db9a6c16b2887a1d.tar.gz linux-3.10-83112e688f5f05dea1e63787db9a6c16b2887a1d.tar.bz2 linux-3.10-83112e688f5f05dea1e63787db9a6c16b2887a1d.zip | |
perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus
With AMD cpu family 15h a unit mask was introduced for the Data Cache
Miss event (0x041/L1-dcache-load-misses). We need to enable bit 0
(first data cache miss or streaming store to a 64 B cache line) of
this mask to proper count data cache misses.
Now we set this bit for all families and models. In case a PMU does
not implement a unit mask for event 0x041 the bit is ignored.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1302913676-14352-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_amd.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index 461f62bbd77..4e1613845b9 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c @@ -8,7 +8,7 @@ static __initconst const u64 amd_hw_cache_event_ids [ C(L1D) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ - [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ + [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |